Renamed FPGA Targets and variables

fpga/makefile

@@ -16,8 +16,8 @@ include $(SOCLABS_NANOSOC_TECH_DIR)/fpga/makefile.fpga_targets
 VIVIADO_VERSION  ?= 2021_1
 
 # NanoSoC Synthesis Properties
-VENDOR           ?= soclabs.org
-NANOSOC_CORE_REV ?= 2
+VENDOR   ?= soclabs.org
+CORE_REV ?= 2
 
 # System Design Filelist
 ifeq ($(QUICKSTART),yes)
@@ -27,7 +27,7 @@ else
 endif
 
 # Top-level of RTL design to Implement
-FPGA_TOP    ?= nanosoc_chip
+COMPONENT_TOP  ?= nanosoc_chip
 
 # Name of Implemented Chip Design (Including Socket IP)
 DESIGN_NAME ?= nanosoc_design
@@ -79,7 +79,7 @@ code:
 	@$(MAKE) -C $(SOCLABS_NANOSOC_TECH_DIR) compile_all_code
 
 # Generate TCL filelist from flists
-nanosoc_flist:
+flist_nanosoc:
 	@mkdir -p $(TCL_FLIST_DIR)
 	@(cd $(TCL_FLIST_DIR); \
 	$(SOCLABS_SOCTOOLS_FLOW_DIR)/bin/filelist_compile.py -t -f $(DESIGN_VC) -o $(TCL_OUTPUT_FILELIST) -r $(IMP_NANOSOC_DIR) -d $(NANOSOC_DEFINES);)
@@ -92,12 +92,12 @@ package_socket:
 package_nanosoc: export FPGA_COMPONENT_FILELIST = $(TCL_OUTPUT_FILELIST)
 package_nanosoc: export FPGA_COMPONENT_LIB      = $(IMP_NANOSOC_DIR)
 package_nanosoc: export FPGA_ACCELERATOR        = $(ACCELERATOR_SUBSYSTEM)
-package_nanosoc: export FPGA_DESIGN_TOP         = $(FPGA_TOP)
+package_nanosoc: export FPGA_COMPONENT_TOP      = $(COMPONENT_TOP)
 package_nanosoc: export FPGA_VENDOR             = $(VENDOR)
-package_nanosoc: export FPGA_CORE_REV           = $(NANOSOC_CORE_REV)
+package_nanosoc: export FPGA_CORE_REV           = $(CORE_REV)
 
 # Package NanoSoC IP
-package_nanosoc: code nanosoc_flist
+package_nanosoc: code flist_nanosoc
 	@echo Packaging NanoSoC
 	@mkdir -p $(RUN_DIR)
 	@cd $(RUN_DIR); vivado -mode batch -source $(SOCLABS_SOCTOOLS_FLOW_DIR)/resources/fpga/package_component.tcl

socdebug_tech @ dd994317

-Subproject commit 6afabad6b246d01a7feb1c4348982eeb9479f5e1
+Subproject commit dd9943174e8cb8953e9b0972f35a72c1e54a9609