Update synopsys dc synthesis flow

flist/nanosoc_ASIC.flist

@@ -31,3 +31,4 @@
 
 // DMAC IP
 -f $(SOCLABS_SLDMA230_TECH_DIR)/flist/sldma230_ip_ASIC.flist
+-f $(SOCLABS_SLDMA350_TECH_DIR)/flist/sldma350_ahb.flist

flows/makefile.asic

@@ -30,7 +30,7 @@ DEFINES_FILE         := $(DEFINES_DIR)/gen_defines.v
 TCL_ASIC_FLIST_DIR        := $(IMP_NANOSOC_ASIC_DIR)/flist
 TCL_ASIC_OUTPUT_FILELIST  := $(TCL_ASIC_FLIST_DIR)/gen_flist.tcl
 GENUS_OUTPUT_FILELIST := $(TCL_ASIC_FLIST_DIR)/genus_flist.tcl
-SYNTHESIS_OUTPUT_FILELIST := $(TCL_ASIC_FLIST_DIR)/synth_flist_copy.sh
+DC_OUTPUT_FILELIST := $(TCL_ASIC_FLIST_DIR)/dc_flist.tcl
 
 # Location of outputs from synthesis
 MEMORIES_DIR		:= $(SOCLABS_PROJECT_DIR)/memories
@@ -55,10 +55,10 @@ PINMAP_FILE           ?= $(TARGET_DIR)/fpga_pinmap.xdc
 # NanoSoC Tech Socket Design Dependencies
 RTL_SOCKET_DIR        := $(SOCLABS_SOCDEBUG_TECH_DIR)/socket/vivado_packages
 
-flist_asic_nanosoc: gen_defs
+flist_dc_nanosoc: gen_defs
 	@mkdir -p $(TCL_ASIC_FLIST_DIR)
 	@(cd $(TCL_ASIC_FLIST_DIR); \
-    $(SOCLABS_SOCTOOLS_FLOW_DIR)/bin/filelist_compile.py -t -s -a -f $(DESIGN_VC) -o $(SYNTHESIS_OUTPUT_FILELIST) -r $(IMP_NANOSOC_ASIC_DIR)/src;)
+    $(SOCLABS_SOCTOOLS_FLOW_DIR)/bin/filelist_compile.py -t -s -a -f $(DESIGN_VC) -o $(DC_OUTPUT_FILELIST) -r $(IMP_NANOSOC_ASIC_DIR)/src;)
 
 flist_genus_nanosoc: gen_defs
 	@mkdir -p $(TCL_ASIC_FLIST_DIR)
@@ -66,34 +66,22 @@ flist_genus_nanosoc: gen_defs
 	$(SOCLABS_SOCTOOLS_FLOW_DIR)/bin/filelist_compile.py -t -g -f $(DESIGN_VC) -o $(GENUS_OUTPUT_FILELIST) -r $(IMP_NANOSOC_DIR)/synthesis/src -d $(NANOSOC_DEFINES);)
 
 
-
-#copy_asic_nanosoc: SHELL:=/bin/bash
-copy_asic_nanosoc: gen_defs flist_asic_nanosoc
-	@mkdir -p $(IMP_NANOSOC_ASIC_DIR)/src
-	@(cd $(IMP_NANOSOC_ASIC_DIR)/src)
-	@(chmod +x $(SYNTHESIS_OUTPUT_FILELIST))
-	@(source $(SYNTHESIS_OUTPUT_FILELIST))
-
-
 gen_memories: bootrom
 	@mkdir -p $(MEMORIES_DIR)
 	@mkdir -p $(RF_DIR)
 	@mkdir -p $(ROM_DIR)
 	echo "Generating register file memory libraries"
-	cd $(RF_DIR); $(PHYS_IP)/arm/tsmc/cln65lp/rf_sp_hdf_hvt_rvt/r0p0/bin/rf_sp_hdf_hvt_rvt ascii -spec $(RF_SPEC_FILE);
+	cd $(RF_DIR); $(PHYS_IP)/arm/tsmc/cln65lp/rf_sp_hdf_hvt_rvt/r0p0/bin/rf_sp_hdf_hvt_rvt all -spec $(RF_SPEC_FILE);
 	cd $(RF_DIR); $(PHYS_IP)/arm/tsmc/cln65lp/rf_sp_hdf_hvt_rvt/r0p0/bin/rf_sp_hdf_hvt_rvt liberty -spec $(RF_SPEC_FILE);
-	cd $(RF_DIR); $(PHYS_IP)/arm/tsmc/cln65lp/rf_sp_hdf_hvt_rvt/r0p0/bin/rf_sp_hdf_hvt_rvt postscript -spec $(RF_SPEC_FILE);
-	cd $(RF_DIR); $(PHYS_IP)/arm/tsmc/cln65lp/rf_sp_hdf_hvt_rvt/r0p0/bin/rf_sp_hdf_hvt_rvt lef-fp -spec $(RF_SPEC_FILE);
-	cd $(RF_DIR); $(PHYS_IP)/arm/tsmc/cln65lp/rf_sp_hdf_hvt_rvt/r0p0/bin/rf_sp_hdf_hvt_rvt verilog -spec $(RF_SPEC_FILE);
 	cd $(ROM_DIR)
 	echo "Generating ROM Libraries"
-	cd $(ROM_DIR); $(PHYS_IP)/arm/tsmc/cln65lp/rom_via_hdd_rvt_rvt/r0p0/bin/rom_via_hdd_rvt_rvt ascii -spec $(ROM_SPEC_FILE) -code_file $(BOOTROM_BIN_FILE);
 	cd $(ROM_DIR); $(PHYS_IP)/arm/tsmc/cln65lp/rom_via_hdd_rvt_rvt/r0p0/bin/rom_via_hdd_rvt_rvt liberty -spec $(ROM_SPEC_FILE) -code_file $(BOOTROM_BIN_FILE);
-	cd $(ROM_DIR); $(PHYS_IP)/arm/tsmc/cln65lp/rom_via_hdd_rvt_rvt/r0p0/bin/rom_via_hdd_rvt_rvt postscript -spec $(ROM_SPEC_FILE) -code_file $(BOOTROM_BIN_FILE);
-	cd $(ROM_DIR); $(PHYS_IP)/arm/tsmc/cln65lp/rom_via_hdd_rvt_rvt/r0p0/bin/rom_via_hdd_rvt_rvt lef-fp -spec $(ROM_SPEC_FILE) -code_file $(BOOTROM_BIN_FILE);
-	cd $(ROM_DIR); $(PHYS_IP)/arm/tsmc/cln65lp/rom_via_hdd_rvt_rvt/r0p0/bin/rom_via_hdd_rvt_rvt verilog -spec $(ROM_SPEC_FILE) -code_file $(BOOTROM_BIN_FILE);
+	cd $(ROM_DIR); $(PHYS_IP)/arm/tsmc/cln65lp/rom_via_hdd_rvt_rvt/r0p0/bin/rom_via_hdd_rvt_rvt all -spec $(ROM_SPEC_FILE) -code_file $(BOOTROM_BIN_FILE);
 	echo "Finished generating memory libraries"
 
+convert_mem_to_db: 
+	lc_shell -no_log -f  $(NANOSOC_SYNTH_DIR)/synopsys_lib_conversion.tcl
+
 syn_genus: 
 	@mkdir -p $(REPORTS_FOLDER)
 	@mkdir -p $(NETLIST_FOLDER)
@@ -101,6 +89,13 @@ syn_genus:
 	cd $(NANOSOC_SYNTH_DIR)
 	@(genus -f $(NANOSOC_SYNTH_DIR)/genus.tcl -log $(SYN_LOGS)/nanosoc_synth)
 
+syn_dc:
+	@mkdir -p $(REPORTS_FOLDER)
+	@mkdir -p $(NETLIST_FOLDER)
+	@mkdir -p $(SYN_LOGS)
+	cd $(NANOSOC_SYNTH_DIR)
+	@(dc_shell -f $(NANOSOC_SYNTH_DIR)/synopsys.tcl -output_log_file $(SYN_LOGS)/nanosoc_synth)
+
 # Clean FPGA Run
 clean_synthesis:
 	@echo Cleaning Previous Runs of $(BOARD_NAME)

sldma350_tech @ d7b4b1b6

-Subproject commit 3f1282ae2c6573b23872f6b2e99cf17c71063887
+Subproject commit d7b4b1b62b891668ca6554fe1806c45ff80ed76d

synthesis/rf_sp_hdf.spec

@@ -21,7 +21,7 @@ mvt =
 name_case = upper
 power_type = otc
 prefix = 
-pwr_gnd_rename = vddpe:VDDPE,vddce:VDDCE,vsse:VSSE
+pwr_gnd_rename = vddpe:VDD,vddce:VDD,vsse:VSS
 retention = on
 right_bus_delim = ]
 ser = none

synthesis/synopsys.tcl

@@ -9,16 +9,17 @@
 # Copyright (C) 2021-3, SoC Labs (www.soclabs.org)
 #-----------------------------------------------------------------------------
 
-set rtlPath $env(SOCLABS_PROJECT_DIR)/imp/ASIC/nanosoc/src/
+set rtlPath $env(SOCLABS_PROJECT_DIR)
+set report_path $env(SOCLABS_PROJECT_DIR)/imp/ASIC/nanosoc/reports/
 set top_module nanosoc_chip_pads
-supress_message = {ELAB-405}
+#supress_message = {ELAB-405}
 #####
 # Set search_path
 #
 # List locations where your standard cell libraries may be located
 #
 #####
-set search_path [list . $search_path $env(PHYS_IP)/arm/tsmc/cln65lp/sc9_base_rvt/r0p0/sdb/ $env(PHYS_IP)/arm/tsmc/cln65lp/sc9_base_rvt/r0p0/db/ $env(SOCLABS_PROJECT_DIR)/memories/rf]
+set search_path [list . $search_path $env(PHYS_IP)/arm/tsmc/cln65lp/sc12_base_rvt/r0p0/sdb/ $env(PHYS_IP)/arm/tsmc/cln65lp/sc12_base_rvt/r0p0/db/ $env(SOCLABS_PROJECT_DIR)/memories/rf $env(SOCLABS_PROJECT_DIR)/memories/bootrom]
 set search_path [concat $rtlPath $search_path]
 ######
 # Set Target Library
@@ -26,7 +27,7 @@ set search_path [concat $rtlPath $search_path]
 # Set a default target library for Design Compiler to target when compiling a design
 #
 ######
-set target_library "sc9_cln65lp_base_rvt_tt_typical_max_1p20v_25c.db RF_LIB_tt_1p20v_1p20v_25c.db"
+set target_library "sc12_cln65lp_base_rvt_ss_typical_max_1p08v_125c.db rf_sp_hdf_ss_1p08v_1p08v_125c.db rom_via_ss_1p08v_1p08v_125c.db"
 
 ######
 # Set Link Library
@@ -34,34 +35,34 @@ set target_library "sc9_cln65lp_base_rvt_tt_typical_max_1p20v_25c.db RF_LIB_tt_1
 # Set a default link library for Design Compiler to target when compiling a design
 #
 ######
-set link_library sc9_cln65lp_base_rvt_tt_typical_max_1p20v_25c.db
+set link_library "sc12_cln65lp_base_rvt_ss_typical_max_1p08v_125c.db rf_sp_hdf_ss_1p08v_1p08v_125c.db rom_via_ss_1p08v_1p08v_125c.db"
 
-#read_file {/home/dwn1c21/SoC-Labs/accelerator-project/imp/ASIC/nanosoc/src/} -autoread -recursive -format verilog -top $top_module
-
-analyze -format sverilog -lib WORK -define POWER_PINS [glob  $env(SOCLABS_PROJECT_DIR)/imp/ASIC/nanosoc/src/*.sv]
-analyze -format verilog -lib WORK -define POWER_PINS [glob  $env(SOCLABS_PROJECT_DIR)/imp/ASIC/nanosoc/src/*.v]
+source $env(SOCLABS_PROJECT_DIR)/imp/ASIC/nanosoc/flist/dc_flist.tcl
 elaborate $top_module -lib WORK
 current_design $top_module
 
 # Link Design
 link
 
-create_clock XTAL1 -period 10 -waveform {0 5}
-set_clock_latency 0.3 XTAL1
-set_input_delay 1.0 -clock XTAL1 [all_inputs]
-set_output_delay 0.7 -clock XTAL1 [all_outputs]
-set_load 0.1 [all_outputs]
-set_max_fanout 1 [all_inputs]
-set_fanout_load 8 [all_outputs]
+read_sdc constraints.sdc 
+
+create_power_domain pd_top -include_scope
+
+add_port_state VSS -state {state1 0.00}
+add_port_state VDD -state {state1 1.08}
+add_port_state VSSIO -state {state1 0.00}
+add_port_state VDDIO -state {state1 3.3}
+
+connect_supply_net pd_top.primary.power -port VDD
+connect_supply_net pd_top.primary.ground -port VSS
 
 compile_ultra -exact_map
 
 write -hierarchy -format verilog -output ./nanosoc_chip_pads.vm
-redirect [format "%s%s%s" ./ $top_module _area.rep] { report_area }
-redirect -append [format "%s%s%s" ./ $top_module _area.rep] { report_reference }
-redirect [format "%s%s%s" ./ $top_module _power.rep] { report_power }
-redirect [format "%s%s%s" ./ $top_module _timing.rep] \
+redirect [format "%s%s%s" $report_path $top_module _area.rep] { report_area }
+redirect -append [format "%s%s%s" $report_path $top_module _area.rep] { report_reference }
+redirect [format "%s%s%s" $report_path $top_module _power.rep] { report_power }
+redirect [format "%s%s%s" $report_path $top_module _timing.rep] \
   { report_timing -path full -max_paths 100 -nets -transition_time -capacitance -significant_digits 3 -nosplit}
 
 
-exit
\ No newline at end of file

synthesis/synopsys_lib_conversion.tcl

+set RF_PATH $env(SOCLABS_PROJECT_DIR)/memories/rf
+
+read_lib $RF_PATH/rf_sp_hdf_ss_1p08v_1p08v_125c.lib
+write_lib RF_LIB_ss_1p08v_1p08v_125c -output $RF_PATH/rf_sp_hdf_ss_1p08v_1p08v_125c.db
+
+read_lib $RF_PATH/rf_sp_hdf_ss_1p08v_1p08v_m40c.lib
+write_lib RF_LIB_ss_1p08v_1p08v_m40c -output $RF_PATH/rf_sp_hdf_ss_1p08v_1p08v_m40c.db
+
+read_lib $RF_PATH/rf_sp_hdf_ff_1p32v_1p32v_125c.lib
+write_lib RF_LIB_ff_1p32v_1p32v_125c -output $RF_PATH/rf_sp_hdf_ff_1p32v_1p32v_125c.db
+
+read_lib $RF_PATH/rf_sp_hdf_ff_1p32v_1p32v_m40c.lib
+write_lib RF_LIB_ff_1p32v_1p32v_m40c -output $RF_PATH/rf_sp_hdf_ff_1p32v_1p32v_m40c.db
+
+read_lib $RF_PATH/rf_sp_hdf_tt_1p20v_1p20v_25c.lib
+write_lib RF_LIB_tt_1p20v_1p20v_25c -output $RF_PATH/rf_sp_hdf_tt_1p20v_1p20v_25c.db
+
+set ROM_PATH $env(SOCLABS_PROJECT_DIR)/memories/bootrom
+
+read_lib $ROM_PATH/rom_via_ss_1p08v_1p08v_125c.lib
+write_lib USERLIB_ss_1p08v_1p08v_125c -output $ROM_PATH/rom_via_ss_1p08v_1p08v_125c.db
+
+read_lib $ROM_PATH/rom_via_ss_1p08v_1p08v_m40c.lib
+write_lib USERLIB_ss_1p08v_1p08v_m40c -output $ROM_PATH/rom_via_ss_1p08v_1p08v_m40c.db
+
+read_lib $ROM_PATH/rom_via_ff_1p32v_1p32v_125c.lib
+write_lib USERLIB_ff_1p32v_1p32v_125c -output $ROM_PATH/rom_via_ff_1p32v_1p32v_125c.db
+
+read_lib $ROM_PATH/rom_via_ff_1p32v_1p32v_m40c.lib
+write_lib USERLIB_ff_1p32v_1p32v_m40c -output $ROM_PATH/rom_via_ff_1p32v_1p32v_m40c.db
+
+read_lib $ROM_PATH/rom_via_tt_1p20v_1p20v_25c.lib
+write_lib USERLIB_tt_1p20v_1p20v_25c -output $ROM_PATH/rom_via_tt_1p20v_1p20v_25c.db
+
+exit
\ No newline at end of file