Updated lint flows

hal/corstone101_ip.bb

@@ -16,59 +16,59 @@ bb_list
 {
     // Exclude APB Timer as Arm IP
     designunit = cmsdk_apb_timer;
-    file = $ARM_IP_LIBRARY_PATH/latest/Corstone-101/logical/cmsdk_apb_timer/verilog/cmsdk_apb_timer.v;
+    file = $ARM_CORSTONE_101_DIR/cmsdk_apb_timer/verilog/cmsdk_apb_timer.v;
     
     // Exclude APB Dual Timer as Arm IP
     designunit = cmsdk_apb_dualtimers;
-    file = $ARM_IP_LIBRARY_PATH/latest/Corstone-101/logical/cmsdk_apb_dualtimers/verilog/cmsdk_apb_dualtimers.v;
+    file = $ARM_CORSTONE_101_DIR/cmsdk_apb_dualtimers/verilog/cmsdk_apb_dualtimers.v;
     
     // Exclude APB UART as Arm IP
     designunit = cmsdk_apb_uart;
-    file = $ARM_IP_LIBRARY_PATH/latest/Corstone-101/logical/cmsdk_apb_uart/verilog/cmsdk_apb_uart.v;
+    file = $ARM_CORSTONE_101_DIR/cmsdk_apb_uart/verilog/cmsdk_apb_uart.v;
     
     // Exclude APB Watchdog as Arm IP
     designunit = cmsdk_apb_watchdog;
-    file = $ARM_IP_LIBRARY_PATH/latest/Corstone-101/logical/cmsdk_apb_watchdog/verilog/cmsdk_apb_watchdog.v;
+    file = $ARM_CORSTONE_101_DIR/cmsdk_apb_watchdog/verilog/cmsdk_apb_watchdog.v;
     
     // Exclude AHB Slave Mux as Arm IP
     designunit = cmsdk_ahb_slave_mux;
-    file = $ARM_IP_LIBRARY_PATH/latest/Corstone-101/logical/cmsdk_ahb_slave_mux/verilog/cmsdk_ahb_slave_mux.v;
+    file = $ARM_CORSTONE_101_DIR/cmsdk_ahb_slave_mux/verilog/cmsdk_ahb_slave_mux.v;
     
     // Exclude AHB Default Slave as Arm IP
     designunit = cmsdk_ahb_default_slave;
-    file = $ARM_IP_LIBRARY_PATH/latest/Corstone-101/logical/cmsdk_ahb_default_slave/verilog/cmsdk_ahb_default_slave.v;
+    file = $ARM_CORSTONE_101_DIR/cmsdk_ahb_default_slave/verilog/cmsdk_ahb_default_slave.v;
     
     // Exclude AHB GPIO as Arm IP
     designunit = cmsdk_ahb_gpio;
-    file = $ARM_IP_LIBRARY_PATH/latest/Corstone-101/logical/cmsdk_ahb_gpio/verilog/cmsdk_ahb_gpio.v;
+    file = $ARM_CORSTONE_101_DIR/cmsdk_ahb_gpio/verilog/cmsdk_ahb_gpio.v;
     
     // Exclude AHB to APB Bridge as Arm IP
     designunit = cmsdk_ahb_to_apb;
-    file = $ARM_IP_LIBRARY_PATH/latest/Corstone-101/logical/cmsdk_ahb_to_apb/verilog/cmsdk_ahb_to_apb.v;
+    file = $ARM_CORSTONE_101_DIR/cmsdk_ahb_to_apb/verilog/cmsdk_ahb_to_apb.v;
     
     // Exclude IOP to GPIO Bridge as Arm IP
     designunit = cmsdk_iop_gpio;
-    file = $ARM_IP_LIBRARY_PATH/latest/Corstone-101/logical/cmsdk_iop_gpio/verilog/cmsdk_iop_gpio.v;
+    file = $ARM_CORSTONE_101_DIR/cmsdk_iop_gpio/verilog/cmsdk_iop_gpio.v;
     
     // Exclude AHB to SRAM Bridge as Arm IP
     designunit = cmsdk_ahb_to_sram;
-    file = $ARM_IP_LIBRARY_PATH/latest/Corstone-101/logical/cmsdk_ahb_to_sram/verilog/cmsdk_ahb_to_sram.v;
+    file = $ARM_CORSTONE_101_DIR/cmsdk_ahb_to_sram/verilog/cmsdk_ahb_to_sram.v;
     
     // Exclude SRAM Model as Arm IP
     designunit = cmsdk_fpga_sram;
-    file = $ARM_IP_LIBRARY_PATH/latest/Corstone-101/logical/models/memories/cmsdk_fpga_sram.v;
+    file = $ARM_CORSTONE_101_DIR/models/memories/cmsdk_fpga_sram.v;
     
     // Exclude APB Slave Mux as Arm IP
     designunit = cmsdk_apb_slave_mux;
-    file = $ARM_IP_LIBRARY_PATH/latest/Corstone-101/logical/cmsdk_apb_slave_mux/verilog/cmsdk_apb_slave_mux.v;
+    file = $ARM_CORSTONE_101_DIR/cmsdk_apb_slave_mux/verilog/cmsdk_apb_slave_mux.v;
     
     // Exclude CMSDK FPGA ROM
     designunit = cmsdk_fpga_rom;
-    file = $ARM_IP_LIBRARY_PATH/latest/Corstone-101/logical/models/memories/cmsdk_fpga_rom.v;
+    file = $ARM_CORSTONE_101_DIR/models/memories/cmsdk_fpga_rom.v;
     
     // Exclude APB Test slave as Arm IP
     designunit = cmsdk_apb_test_slave;
-    file = $ARM_IP_LIBRARY_PATH/latest/Corstone-101/logical/cmsdk_apb_subsystem/verilog/cmsdk_apb_test_slave.v;
+    file = $ARM_CORSTONE_101_DIR/cmsdk_apb_subsystem/verilog/cmsdk_apb_test_slave.v;
     
     // Exclude Pads
     designunit = PAD_INOUT8MA_NOE;

makefile

@@ -83,7 +83,6 @@ BOOTROM_ADDRW     ?= 8
 BOOTROM_HEX       ?= $(SOCLABS_NANOSOC_TECH_DIR)/testcodes/bootloader/$(BOOTLOADER).hex
 BOOTROM_BUILD_DIR ?= $(SOCLABS_PROJECT_DIR)/system/src/bootrom
 
-QUICKSTART ?= no
 
 ACCELERATOR ?= yes
 
@@ -94,17 +93,25 @@ ifeq ($(ACCELERATOR),yes)
 	DEFINES_VC += +define+ACCELERATOR_SUBSYSTEM
 endif
 
+QUICKSTART ?= no
+
 # System Design Filelist
 ifeq ($(QUICKSTART),yes)
-	DESIGN_VC   ?= $(SOCLABS_PROJECT_DIR)/flist/project/top_qs.flist
-	TBENCH_VC   ?= $(SOCLABS_PROJECT_DIR)/flist/project/top_qs.flist
-	TB_TOP      ?= nanosoc_tb_qs
+	DESIGN_VC            ?= $(SOCLABS_PROJECT_DIR)/flist/project/top_qs.flist
+	TBENCH_VC            ?= $(SOCLABS_PROJECT_DIR)/flist/project/top_qs.flist
+	ARM_CORSTONE_101_DIR ?= $(ARM_IP_LIBRARY_PATH)/latest/Cortex-M0-QS/Corstone-101-logical
+	ARM_CORTEX_M0_DIR    ?= $(ARM_IP_LIBRARY_PATH)/latest/Cortex-M0-QS/Cortex-M0-logical
+	TB_TOP               ?= nanosoc_tb_qs
 else
-	DESIGN_VC   ?= $(SOCLABS_PROJECT_DIR)/flist/project/top.flist
-	TBENCH_VC   ?= $(SOCLABS_PROJECT_DIR)/flist/project/top.flist
-	TB_TOP      ?= nanosoc_tb
+	DESIGN_VC            ?= $(SOCLABS_PROJECT_DIR)/flist/project/top.flist
+	TBENCH_VC            ?= $(SOCLABS_PROJECT_DIR)/flist/project/top.flist
+	ARM_CORSTONE_101_DIR ?= $(ARM_IP_LIBRARY_PATH)/latest/Corstone-101/logical
+	ARM_CORTEX_M0_DIR    ?= $(ARM_IP_LIBRARY_PATH)/latest/Cortex-M0/logical
+	TB_TOP               ?= nanosoc_tb
 endif
 
+export ARM_CORTEX_M0_DIR
+export ARM_CORSTONE_101_DIR
 
 # Simulator type (mti/vcs/xm)
 SIMULATOR   = mti

slcorem0_tech @ c548cd60

-Subproject commit b5948804f2ab71cd588d4c1381f88854f0d4dc50
+Subproject commit c548cd60119c081441ab4b644a0083dc4f684c92

sldma230_tech @ 9ccb88a6

-Subproject commit 1c59ebb260edc4cf815e1e2f2be562dfb1c4a46b
+Subproject commit 9ccb88a6057f003c58f80168d8dca64daf76d08f

socdebug_tech @ 3ad54801

-Subproject commit cb454e4c550ff291d83b08b840c8a2399f4b6d4e
+Subproject commit 3ad5480136eb91bf2c17da27c07a0bda8e2fcec3