Add flist to tcl python script

fpga_imp/scripts/flist_to_tcl.py

+import argparse
+import os
+parser = argparse.ArgumentParser(description="Take flist file for verilog simulation and convert to tcl readable",
+                                 formatter_class=argparse.ArgumentDefaultsHelpFormatter)
+parser.add_argument("-i", "--input", help="input flist file")
+parser.add_argument("-o", "--output", help="output tcl file")
+args = parser.parse_args()
+config = vars(args)
+
+if not os.path.exists(config["output"]):
+    outfile = open(config["output"], "a")
+
+
+    for line in open(config["input"]):
+        li = line.strip()
+        if not li.startswith("//"):
+            if li.endswith(".v"):
+                output = (line.rstrip()).replace("$","read_verilog $env")
+                outfile.write(output+'\n')
+
+
+    outfile.close()
+else:
+    print("ERROR: Output file already exists")
+
+