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Commit 7010463d authored by dam1n19's avatar dam1n19
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SOC1-167: Added Bootrom compile to CI script

parent 469f87b5
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...@@ -15,5 +15,4 @@ system/testcodes/*/*.lst ...@@ -15,5 +15,4 @@ system/testcodes/*/*.lst
system/testcodes/*/*.o system/testcodes/*/*.o
# Bootrom removal # Bootrom removal
/system/src/bootrom/verilog/* /system/src/bootrom/
/system/src/bootrom/bintxt/* \ No newline at end of file
...@@ -35,6 +35,9 @@ build-job-Z2: # This job runs in the build stage, which runs first. ...@@ -35,6 +35,9 @@ build-job-Z2: # This job runs in the build stage, which runs first.
- tar -xf PL230-r0p0-02rel2-1.tar.gz - tar -xf PL230-r0p0-02rel2-1.tar.gz
# move to fpga_imp directory and run the fpga build script for pynq z2 # move to fpga_imp directory and run the fpga build script for pynq z2
- cd ../../nanosoc/system/fpga_imp/ - cd ../../nanosoc/system/fpga_imp/
- source ../../set_env.sh
- mkdir -p $NANOSOC_TECH_DIR/system/src/bootrom
- make -C $NANOSOC_TECH_DIR/system bootrom BOOTROM_BUILD_DIR=$NANOSOC_TECH_DIR/system/src/bootrom
- if source ./build_fpga_pynq_z2.scr; then echo "Vivado Finished"; fi - if source ./build_fpga_pynq_z2.scr; then echo "Vivado Finished"; fi
- FILE=./pynq_export/pz2/pynq/overlays/soclabs/design_1.bit - FILE=./pynq_export/pz2/pynq/overlays/soclabs/design_1.bit
- if test -f "$FILE"; then - if test -f "$FILE"; then
...@@ -68,6 +71,9 @@ build-job-ZCU104: # This job runs in the build stage, which runs first. ...@@ -68,6 +71,9 @@ build-job-ZCU104: # This job runs in the build stage, which runs first.
- tar -xf PL230-r0p0-02rel2-1.tar.gz - tar -xf PL230-r0p0-02rel2-1.tar.gz
# move to fpga_imp directory and run the fpga build script for pynq z2 # move to fpga_imp directory and run the fpga build script for pynq z2
- cd ../../nanosoc/system/fpga_imp/ - cd ../../nanosoc/system/fpga_imp/
- source ../../set_env.sh
- mkdir -p $NANOSOC_TECH_DIR/system/src/bootrom
- make -C $NANOSOC_TECH_DIR/system bootrom BOOTROM_BUILD_DIR=$NANOSOC_TECH_DIR/system/src/bootrom
- if source ./build_fpga_pynq_zcu104.scr; then echo "Vivado Finished"; fi - if source ./build_fpga_pynq_zcu104.scr; then echo "Vivado Finished"; fi
- FILE=./pynq_export/pz104/pynq/overlays/soclabs/design_1.bit - FILE=./pynq_export/pz104/pynq/overlays/soclabs/design_1.bit
- if test -f "$FILE"; then - if test -f "$FILE"; then
......
...@@ -74,8 +74,10 @@ ADP_PATH := $(shell realpath $(ADP_FILE)) ...@@ -74,8 +74,10 @@ ADP_PATH := $(shell realpath $(ADP_FILE))
ADP_OPTIONS := -define ADP_FILE=\"$(ADP_PATH)\" ADP_OPTIONS := -define ADP_FILE=\"$(ADP_PATH)\"
# Bootrom Parameters: # Bootrom Parameters:
# Boot Loader image
BOOTLOADER ?= bootloader
BOOTROM_ADDRW ?= 8 BOOTROM_ADDRW ?= 8
BOOTROM_HEX ?= $(NANOSOC_TECH_DIR)/system/testcodes/bootloader/bootloader.hex BOOTROM_HEX ?= $(NANOSOC_TECH_DIR)/system/testcodes/bootloader/$(BOOTLOADER).hex
BOOTROM_BUILD_DIR ?= $(PROJ_SYS_DIR)/bootrom BOOTROM_BUILD_DIR ?= $(PROJ_SYS_DIR)/bootrom
...@@ -111,8 +113,7 @@ VCS_VC_OPTIONS = -f $(TBENCH_VC) $(ACCELERATOR_VC) ...@@ -111,8 +113,7 @@ VCS_VC_OPTIONS = -f $(TBENCH_VC) $(ACCELERATOR_VC)
XMSIM_OPTIONS = -unbuffered -status -LICQUEUE -f xmsim.args -cdslib cds.lib -hdlvar hdl.var -NBASYNC XMSIM_OPTIONS = -unbuffered -status -LICQUEUE -f xmsim.args -cdslib cds.lib -hdlvar hdl.var -NBASYNC
XM_VC_OPTIONS = $(TBENCH_VC) $(ACCELERATOR_VC) $(ADP_OPTIONS) XM_VC_OPTIONS = $(TBENCH_VC) $(ACCELERATOR_VC) $(ADP_OPTIONS)
# Boot Loader image
BOOTLOADER = bootloader
# Debug Tester image # Debug Tester image
DEBUGTESTER = debugtester DEBUGTESTER = debugtester
...@@ -277,26 +278,21 @@ bootrom: ...@@ -277,26 +278,21 @@ bootrom:
echo Compile done ;\ echo Compile done ;\
ls > /dev/null ;\ ls > /dev/null ;\
echo Copy $(BOOTLOADER).hex ;\ echo Copy $(BOOTLOADER).hex ;\
if [ -e $(BOOTLOADER).hex ] ; then \
cp $(BOOTLOADER).hex $(SIM_DIR)/$(BOOTLOADER).hex ;\
else \
while [ ! -e $(BOOTLOADER).hex ] ; do \ while [ ! -e $(BOOTLOADER).hex ] ; do \
echo Wait for hex file ...; \ echo Wait for hex file ...; \
ls > /dev/null; \ ls > /dev/null; \
sleep 5; \ sleep 5; \
done; \ done; \
if [ -e $(BOOTLOADER).hex ] ; then \ if [ ! -e $(BOOTLOADER).hex ] ; then \
cp $(BOOTLOADER).hex $(SIM_DIR)/$(BOOTLOADER).hex ;\
else \
echo Problem reading hex file ;\ echo Problem reading hex file ;\
exit 1; \ exit 1; \
fi ;\ fi ;\
fi ;\ mkdir -p $(BOOTROM_BUILD_DIR)/verilog/ ;\
cp $(BOOTLOADER).hex $(SIM_DIR)/$(BOOTLOADER).hex ;\ mkdir -p $(BOOTROM_BUILD_DIR)/bintxt/ ;\
mkdir -p $(PROJ_SYS_DIR)/bootrom/verilog/ ;\ python3 bootrom_gen.py -a $(BOOTROM_ADDRW) -i $(BOOTLOADER).hex -v $(BOOTROM_BUILD_DIR)/verilog/bootrom.v -b $(BOOTROM_BUILD_DIR)/bintxt/bootrom.bintxt )
mkdir -p $(PROJ_SYS_DIR)/bootrom/bintxt/ ;\ ifneq ($(PROJECT_DIR),)
python3 bootrom_gen.py -a $(BOOTROM_ADDRW) -i $(BOOTLOADER).hex -v $(BOOTROM_BUILD_DIR)/verilog/bootrom.v -b $(BOOTROM_BUILD_DIR)/bintxt/bootrom.bintxt ;\ cp $(BOOTROM_HEX) $(SIM_DIR)/$(BOOTLOADER).hex
cd $(SIM_DIR) ) endif
# Compile test code # Compile test code
# Note : The use of ls after compile allows the computing server to sync up # Note : The use of ls after compile allows the computing server to sync up
...@@ -409,14 +405,14 @@ v2html: ...@@ -409,14 +405,14 @@ v2html:
# Remove all software compilation results # Remove all software compilation results
clean_all_code: clean_all_code:
@(cd $(NANOSOC_SW_DIR)/debug_tester ; make clean; cd $(SIM_DIR); ) @(cd $(NANOSOC_SW_DIR)/debug_tester ; make clean; )
@(cd $(TESTCODES_DIR)/$(BOOTLOADER) ; make clean; cd $(SIM_DIR); ) @(cd $(TESTCODES_DIR)/$(BOOTLOADER) ; make clean; )
for thistest in $(TEST_LIST) ; do \ for thistest in $(TEST_LIST) ; do \
echo Cleaning $$thistest ... ; \ echo Cleaning $$thistest ... ; \
cd $(TESTCODES_DIR)/$$thistest ; \ cd $(TESTCODES_DIR)/$$thistest ; \
make clean; \ make clean; \
cd $(SIM_DIR); \
done done
@rm -rf $(BOOTROM_BUILD_DIR)
# Remove only bootloader and default selected test # Remove only bootloader and default selected test
clean_code: clean_code:
......
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