Linted Debug Subsystem

hal/nanosoc_ip.waive

@@ -56,10 +56,23 @@ lint_checking designunit = nanosoc_ss_interconnect
     // Not Top-level in design_info
     TPOUNR off;
     
-    // System Width Parameters Unused (Interconenct generated from Arm Script)
+    // System Width Parameters Unused (Interconnect generated from Arm Script)
     USEPAR {"SYS_ADDR_W|SYS_DATA_W"} off;
 }
 
+lint_checking designunit = nanosoc_ss_debug
+{    
+    // Not Top-level in design_info
+    TPOUNR off;
+    
+    // FT1248 can be a one-bit bus
+    ONPNSG {"FT_"} off;
+    
+    // Word Address Used only on APB
+    USEPRT {"DEBUG_PADDR"} off;
+    
+}
+
 lint_checking designunit = nanosoc_region_bootrom_0
 {   
     // Some Bits of AHB Signals not Used

system/nanosoc_subsystems/debug/verilog/nanosoc_ss_debug.v

@@ -14,6 +14,9 @@ module nanosoc_ss_debug #(
     parameter         SYS_ADDR_W    = 32,  // System Address Width
     parameter         SYS_DATA_W    = 32,  // System Data Width
     
+    parameter         APB_ADDR_W    = 12,  // APB Address Width
+    parameter         APB_DATA_W    = 32,  // APB Data Width
+    
     // SoCDebug Parameters
     parameter         PROMPT_CHAR   = "]",
     parameter integer FT1248_WIDTH	= 1, // FTDI Interface 1,2,4 width supported
@@ -28,25 +31,25 @@ module nanosoc_ss_debug #(
     input  wire                     SYS_PRESETn,
     
     // AHB-lite Master Interface - ADP
-    output wire              [31:0] DEBUG_HADDR,
+    output wire    [SYS_ADDR_W-1:0] DEBUG_HADDR,
     output wire              [ 2:0] DEBUG_HBURST,
     output wire                     DEBUG_HMASTLOCK,
     output wire              [ 3:0] DEBUG_HPROT,
     output wire              [ 2:0] DEBUG_HSIZE,
     output wire              [ 1:0] DEBUG_HTRANS,
-    output wire              [31:0] DEBUG_HWDATA,
+    output wire    [SYS_DATA_W-1:0] DEBUG_HWDATA,
     output wire                     DEBUG_HWRITE,
-    input  wire              [31:0] DEBUG_HRDATA,
+    input  wire    [SYS_DATA_W-1:0] DEBUG_HRDATA,
     input  wire                     DEBUG_HREADY,
     input  wire                     DEBUG_HRESP,
     
     // APB Slave Interface - USRT
     input  wire                     DEBUG_PSEL,      // Device select
-    input  wire              [11:0] DEBUG_PADDR,     // Address
+    input  wire    [APB_ADDR_W-1:0] DEBUG_PADDR,     // Address
     input  wire                     DEBUG_PENABLE,   // Transfer control
     input  wire                     DEBUG_PWRITE,    // Write control
-    input  wire              [31:0] DEBUG_PWDATA,    // Write data
-    output wire              [31:0] DEBUG_PRDATA,    // Read data
+    input  wire    [APB_DATA_W-1:0] DEBUG_PWDATA,    // Write data
+    output wire    [APB_DATA_W-1:0] DEBUG_PRDATA,    // Read data
     output wire                     DEBUG_PREADY,    // Device ready
     output wire                     DEBUG_PSLVERR,   // Device error response
     
@@ -63,7 +66,10 @@ module nanosoc_ss_debug #(
     output wire               [7:0] GPO8,
     input  wire               [7:0] GPI8
 );
-
+    
+    //---------------------------
+    // SoCDebug Instantiation
+    //---------------------------
     socdebug_ahb #(
         .PROMPT_CHAR(PROMPT_CHAR),
         .FT1248_WIDTH(FT1248_WIDTH),
@@ -90,7 +96,7 @@ module nanosoc_ss_debug #(
         .PCLKG(SYS_PCLKG),
         .PRESETn(SYS_PRESETn),
         .PSEL_i(DEBUG_PSEL),
-        .PADDR_i(DEBUG_PADDR[11:2]),
+        .PADDR_i(DEBUG_PADDR[APB_ADDR_W-1:2]),
         .PENABLE_i(DEBUG_PENABLE),
         .PWRITE_i(DEBUG_PWRITE),
         .PWDATA_i(DEBUG_PWDATA),

system/nanosoc_system/verilog/nanosoc_system.v

@@ -542,6 +542,10 @@ module nanosoc_system #(
         .SYS_ADDR_W(SYS_ADDR_W),
         .SYS_DATA_W(SYS_DATA_W),
         
+        // APB Parameters
+        .APB_ADDR_W(APB_ADDR_W),
+        .APB_DATA_W(APB_DATA_W),
+        
         // SoCDebug Parameters
         .PROMPT_CHAR(PROMPT_CHAR),
         .FT1248_WIDTH(FT1248_WIDTH),