Add Icarus Verilog Support

flows/makefile.simulate

@@ -34,6 +34,10 @@ endif
 XMSIM_OPTIONS  = -unbuffered -64bit -status -LICQUEUE -f xmsim.args -cdslib cds.lib -hdlvar hdl.var -NBASYNC
 XM_VC_OPTIONS  = -f $(TBENCH_VC) $(ADP_OPTIONS) 
 
+# Icarus Verilog options
+IVERILOG_OPTIONS = -g2005-sv -DVCD_SIM
+
+
 # ------- Cocotb Variables -----------
 # Convert Simulator Name for Cocotb
 COCOTB_SIMULATOR ?= questa
@@ -76,6 +80,7 @@ sim: sim_$(SIMULATOR)
 compile_mti: NANOSOC_DEFINES += IMEM_0_RAM_PRELOAD
 compile_vcs: NANOSOC_DEFINES += IMEM_0_RAM_PRELOAD
 compile_xm:  NANOSOC_DEFINES += IMEM_0_RAM_PRELOAD
+compile_iverilog: NANOSOC_DEFINES += IMEM_0_RAM_PRELOAD
 
 
 # Generate verilog .vc filelist from flists
@@ -159,6 +164,18 @@ lib_mti :
 	  vlib  $(SIM_DIR)/work; \
 	fi
 
+# ------- Icarus -----------
+
+# Compile RTL
+compile_iverilog: bootrom gen_defs flist_vfiles_nanosoc
+	cd $(SIM_DIR); iverilog $(IVERILOG_OPTIONS) -o nanosoc_chip_pads -c tbench.vc
+
+run_iverilog: code compile_iverilog
+	cd $(SIM_DIR); vvp -l $(SIM_DIR)/logs/run_$(TESTNAME).log nanosoc_chip_pads;
+
+sim_iverilog: run_iverilog
+	cd $(SIM_DIR); gtkwave waves.vcd
+
 # Generate Make filelist from flists
 flist_makefile_nanosoc: gen_defs
 	@mkdir -p $(COCOTB_DIR)

verif/tb/verilog/nanosoc_tb.v

@@ -117,7 +117,7 @@ initial
 `ifdef VCD_SIM
 initial begin
   $dumpfile("waves.vcd");
-  $dumpvars(6,u_nanosoc_chip_pads);
+  $dumpvars(0,u_nanosoc_chip_pads);
   end
 `endif // VCD_SIM