Add ASIC flow to flist makefiles

flows/makefile.fpga

@@ -39,6 +39,7 @@ DEFINES_FILE         := $(DEFINES_DIR)/gen_defines.v
 # Name of generated filelist by python script
 TCL_FLIST_DIR        := $(IMP_NANOSOC_DIR)/flist
 TCL_OUTPUT_FILELIST  := $(TCL_FLIST_DIR)/gen_flist.tcl
+GENUS_OUTPUT_FILELIST := $(TCL_FLIST_DIR)/genus_flist.tcl
 
 # NanoSoC Tech Flow Dependencies
 NANOSOC_FPGA_FLOW_DIR := $(SOCLABS_NANOSOC_TECH_DIR)/fpga
@@ -69,6 +70,12 @@ flist_tcl_nanosoc: gen_defs
 	@(cd $(TCL_FLIST_DIR); \
 	$(SOCLABS_SOCTOOLS_FLOW_DIR)/bin/filelist_compile.py -t -f $(DESIGN_VC) -o $(TCL_OUTPUT_FILELIST) -r $(IMP_NANOSOC_DIR)/src -d $(NANOSOC_DEFINES);)
 
+flist_genus_nanosoc: gen_defs
+	@mkdir -p $(TCL_FLIST_DIR)
+	@(cd $(TCL_FLIST_DIR); \
+	$(SOCLABS_SOCTOOLS_FLOW_DIR)/bin/filelist_compile.py -t -g -f $(DESIGN_VC) -o $(GENUS_OUTPUT_FILELIST) -r $(IMP_NANOSOC_DIR)/synthesis/src -d $(NANOSOC_DEFINES);)
+
+
 # Package NanoSoC Socket Components
 package_socket:
 	@$(MAKE) -C $(SOCLABS_SOCDEBUG_TECH_DIR)/fpga package_socket IMP_SOCKET_DIR=$(IMP_SOCKET_DIR) RTL_SOCKET_DIR=$(RTL_SOCKET_DIR)

makefile

@@ -25,6 +25,8 @@ ACCELERATOR ?= yes
 # Is the Arm QuickStart being used?
 QUICKSTART ?= no
 
+ASIC ?= no
+
 #-------------------------------------
 # - Directory Setups
 #-------------------------------------
@@ -70,13 +72,20 @@ ifeq ($(QUICKSTART),yes)
 	ARM_CORSTONE_101_DIR ?= $(ARM_IP_LIBRARY_PATH)/latest/Cortex-M0-QS/Corstone-101-logical
 	ARM_CORTEX_M0_DIR    ?= $(ARM_IP_LIBRARY_PATH)/latest/Cortex-M0-QS/Cortex-M0-logical
 	TB_TOP               ?= nanosoc_tb_qs
-else
-	DESIGN_VC            ?= $(SOCLABS_PROJECT_DIR)/flist/project/top.flist
-	TBENCH_VC            ?= $(SOCLABS_PROJECT_DIR)/flist/project/top.flist
-	ARM_CORSTONE_101_DIR ?= $(ARM_IP_LIBRARY_PATH)/latest/Corstone-101/logical
-	ARM_CORTEX_M0_DIR    ?= $(ARM_IP_LIBRARY_PATH)/latest/Cortex-M0/logical
-	TB_TOP               ?= nanosoc_tb
-	NANOSOC_DEFINES      += DMAC_0_PL230
+else 
+	ifeq ($(ASIC),yes)
+		DESIGN_VC            ?= $(SOCLABS_PROJECT_DIR)/flist/project/top_ASIC.flist
+		ARM_CORSTONE_101_DIR ?= $(ARM_IP_LIBRARY_PATH)/latest/Corstone-101/logical
+		ARM_CORTEX_M0_DIR    ?= $(ARM_IP_LIBRARY_PATH)/latest/Cortex-M0/logical
+		NANOSOC_DEFINES      += DMAC_0_PL230
+	else
+		DESIGN_VC            ?= $(SOCLABS_PROJECT_DIR)/flist/project/top.flist
+		TBENCH_VC            ?= $(SOCLABS_PROJECT_DIR)/flist/project/top.flist
+		ARM_CORSTONE_101_DIR ?= $(ARM_IP_LIBRARY_PATH)/latest/Corstone-101/logical
+		ARM_CORTEX_M0_DIR    ?= $(ARM_IP_LIBRARY_PATH)/latest/Cortex-M0/logical
+		TB_TOP               ?= nanosoc_tb
+		NANOSOC_DEFINES      += DMAC_0_PL230
+	endif
 endif
 
 # Make variables visible to target shells

synthesis/genus.tcl

-set_db init_lib_search_path $::env(PROJECT_DIR)/r9p0-00eac0/lib/
-set_db library sc7_ce018fg_base_rvt_ff_typical_min_1p98v_85c.lib
+set_db init_lib_search_path $::env(PHYS_IP)/arm/tsmc/cln65lp/sc9_base_rvt/r0p0/lib/
+set_db library sc9_cln65lp_base_rvt_tt_typical_max_1p20v_25c.lib
 
-set_db init_hdl_search_path $::env(SOCLABS_NANOSOC_TECH_DIR)/system/src/nanosoc_ahb_busmatrix/verilog/nanosoc_ahb32_4x7_busmatrix/
-
-read_hdl nanosoc_ahb32_4x7_arbiter.v
-read_hdl nanosoc_ahb32_4x7_busmatrix.v
-read_hdl nanosoc_ahb32_4x7_busmatrix_default_slave.v
-read_hdl nanosoc_ahb32_4x7_busmatrix_lite.v
-read_hdl nanosoc_ahb32_4x7_inititator_input.v
-read_hdl nanosoc_ahb32_4x7_matrix_decode_adp.v
-read_hdl nanosoc_ahb32_4x7_matrix_decode_cpu.v
-read_hdl nanosoc_ahb32_4x7_matrix_decode_dma.v
-read_hdl nanosoc_ahb32_4x7_matrix_decode_dma2.v
-read_hdl nanosoc_ahb32_4x7_target_output.v
-
-set_db init_hdl_search_path $::env(ARM_IP_LIBRARY_PATH)/latest/Cortex-M0/logical/
-
-### Cortex-M0 rtl source build
-read_hdl ./cortexm0_dap/verilog/cm0_dap_ap_cdc.v
-read_hdl ./cortexm0_dap/verilog/cm0_dap_ap_mast.v
-read_hdl ./cortexm0_dap/verilog/cm0_dap_dp_cdc.v
-read_hdl ./cortexm0_dap/verilog/cm0_dap_dp_jtag.v
-read_hdl ./cortexm0_dap/verilog/cm0_dap_dp.v
-read_hdl ./cortexm0_dap/verilog/cm0_dap_ap.v
-read_hdl ./cortexm0_dap/verilog/cm0_dap_dp_pwr.v
-read_hdl ./cortexm0_dap/verilog/cm0_dap_dp_sw.v
-read_hdl ./cortexm0_dap/verilog/CORTEXM0DAP.v
-
-read_hdl ./cortexm0/verilog/cm0_core_alu.v
-read_hdl ./cortexm0/verilog/cm0_core_ctl.v
-read_hdl ./cortexm0/verilog/cm0_core_dec.v
-read_hdl ./cortexm0/verilog/cm0_core_gpr.v
-read_hdl ./cortexm0/verilog/cm0_core_mul.v
-read_hdl ./cortexm0/verilog/cm0_core_pfu.v
-read_hdl ./cortexm0/verilog/cm0_core_psr.v
-read_hdl ./cortexm0/verilog/cm0_core_spu.v
-read_hdl ./cortexm0/verilog/cm0_core.v
-read_hdl ./cortexm0/verilog/cm0_dbg_bpu.v
-read_hdl ./cortexm0/verilog/cm0_dbg_ctl.v
-read_hdl ./cortexm0/verilog/cm0_dbg_dwt.v 
-read_hdl ./cortexm0/verilog/cm0_dbg_if.v 
-read_hdl ./cortexm0/verilog/cm0_dbg_sel.v 
-read_hdl ./cortexm0/verilog/cm0_matrix.v 
-read_hdl ./cortexm0/verilog/cm0_matrix_sel.v 
-read_hdl ./cortexm0/verilog/cm0_nvic.v 
-read_hdl ./cortexm0/verilog/cm0_nvic_main.v
-read_hdl ./cortexm0/verilog/cm0_nvic_reg.v
-read_hdl ./cortexm0/verilog/cm0_tarmac.v
-read_hdl ./cortexm0/verilog/cm0_top.v
-read_hdl ./cortexm0/verilog/cm0_top_clk.v 
-read_hdl ./cortexm0/verilog/cm0_top_dbg.v 
-read_hdl ./cortexm0/verilog/cm0_top_sys.v 
-read_hdl ./cortexm0/verilog/CORTEXM0.v
-
-read_hdl ./cortexm0_integration/verilog/cortexm0_pmu.v
-read_hdl ./cortexm0_integration/verilog/cortexm0_rst_ctl.v 
-read_hdl ./cortexm0_integration/verilog/cortexm0_wic.v
-read_hdl ./cortexm0_integration/verilog/CORTEXM0INTEGRATION.v 
-
-set_db init_hdl_search_path $::env(ARM_IP_LIBRARY_PATH)/latest/Cortex-M0/logical/models/cells/
-
-read_hdl cm0_rst_sync.v
-read_hdl cm0_rst_send_set.v
-read_hdl cm0_dbg_reset_sync.v
-read_hdl cm0_acg.v
-read_hdl cm0_pmu_sync_set.v
-read_hdl cm0_pmu_sync_reset.v
-read_hdl cm0_pmu_cdc_send_set.v
-read_hdl cm0_pmu_cdc_send_reset.v
-read_hdl cm0_pmu_acg.v
-
-set_db init_hdl_search_path $::env(ARM_IP_LIBRARY_PATH)/latest/Corstone-101/logical/
-
-read_hdl  ./cmsdk_ahb_gpio/verilog/cmsdk_ahb_to_iop.v
-read_hdl  ./cmsdk_ahb_gpio/verilog/cmsdk_ahb_gpio.v
-read_hdl  ./cmsdk_iop_gpio/verilog/cmsdk_iop_gpio.v
-read_hdl  ./cmsdk_apb_timer/verilog/cmsdk_apb_timer.v 
-read_hdl  ./cmsdk_apb_dualtimers/verilog/cmsdk_apb_dualtimers.v 
-read_hdl  ./cmsdk_apb_dualtimers/verilog/cmsdk_apb_dualtimers_defs.v 
-read_hdl  ./cmsdk_apb_dualtimers/verilog/cmsdk_apb_dualtimers_frc.v 
-read_hdl  ./cmsdk_apb_watchdog/verilog/cmsdk_apb_watchdog.v 
-read_hdl  ./cmsdk_apb_watchdog/verilog/cmsdk_apb_watchdog_defs.v 
-read_hdl  ./cmsdk_apb_watchdog/verilog/cmsdk_apb_watchdog_frc.v 
-read_hdl  ./cmsdk_apb_uart/verilog/cmsdk_apb_uart.v 
-read_hdl  ./cmsdk_ahb_default_slave/verilog/cmsdk_ahb_default_slave.v
-read_hdl  ./cmsdk_ahb_slave_mux/verilog/cmsdk_ahb_slave_mux.v 
-read_hdl  ./cmsdk_ahb_to_apb/verilog/cmsdk_ahb_to_apb.v 
-read_hdl  ./cmsdk_apb_slave_mux/verilog/cmsdk_apb_slave_mux.v 
-read_hdl  ./cmsdk_apb_subsystem/verilog/cmsdk_apb_subsystem.v 
-read_hdl  ./cmsdk_apb_subsystem/verilog/cmsdk_apb_test_slave.v 
-read_hdl  ./cmsdk_apb_subsystem/verilog/cmsdk_irq_sync.v 
-read_hdl  ./cmsdk_ahb_master_mux/verilog/cmsdk_ahb_master_mux.v 
-read_hdl  ./models/clkgate/cmsdk_clock_gate.v
-read_hdl  ./cmsdk_ahb_to_sram/verilog/cmsdk_ahb_to_sram.v
-read_hdl  ./models/memories/cmsdk_ahb_rom.v
-read_hdl  ./models/memories/cmsdk_ahb_ram.v
-read_hdl  ./models/memories/cmsdk_fpga_rom.v
-read_hdl  ./models/memories/cmsdk_fpga_sram.v
-read_hdl  ./models/memories/cmsdk_ahb_memory_models_defs.v
-
-set_db init_hdl_search_path $::env(SOCLABS_NANOSOC_TECH_DIR)/system/test_io/verilog/
-
-read_hdl  nanosoc_ft1248_stream_io_v1_0.v
-read_hdl  nanosoc_adp_control_v1_0.v
-read_hdl  nanosoc_adp_manager.v
-
-set_db init_hdl_search_path $::env(SOCLABS_NANOSOC_TECH_DIR)/system/src/
-
-read_hdl ./verilog/nanosoc_ahb_bootrom.v
-read_hdl ./verilog/nanosoc_ahb_cs_rom_table.v
-read_hdl ./verilog/nanosoc_apb_subsystem.v
-read_hdl ./verilog/nanosoc_apb_usrt.v
-read_hdl ./verilog/nanosoc_chip.v
-read_hdl ./verilog/nanosoc_chip_pads.v
-read_hdl ./verilog/nanosoc_cpu.v
-read_hdl ./verilog/nanosoc_mcu_clkctrl.v
-read_hdl ./verilog/nanosoc_mcu_pin_mux.v
-read_hdl ./verilog/nanosoc_mcu_sysctrl.v
-read_hdl ./verilog/nanosoc_sys_ahb_decode.v
-read_hdl ./verilog/nanosoc_sysio.v
-read_hdl ./bootrom/verilog/bootrom.v
-
-#set_db init_hdl_search_path $::env(ARM_IP_LIBRARY_PATH)/latest/DMA-230/
-set_db init_hdl_search_path $::env(SOCLABS_NANOSOC_TECH_DIR)/system/defines/
-
-read_hdl  pl230_defs.v
-read_hdl $::env(ARM_IP_LIBRARY_PATH)/latest/DMA-230/logical/pl230_ahb_ctrl.v
-read_hdl $::env(ARM_IP_LIBRARY_PATH)/latest/DMA-230/logical/pl230_apb_regs.v
-read_hdl $::env(ARM_IP_LIBRARY_PATH)/latest/DMA-230/logical/pl230_dma_data.v
-read_hdl $::env(ARM_IP_LIBRARY_PATH)/latest/DMA-230/logical/pl230_udma.v
-read_hdl $::env(ARM_IP_LIBRARY_PATH)/latest/DMA-230/logical/pl230_undefs.v
+source $::env(SOCLABS_PROJECT_DIR)/imp/fpga/nanosoc/flist/genus_flist.tcl
 
 elaborate nanosoc_chip_pads