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Commit 43092cb3 authored by Daniel Newbrook's avatar Daniel Newbrook
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Update backend flow

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ASIC/44pin/Cadence/scripts/genus.tcl
+ 1
− 0
View file @ 43092cb3
......@@ -83,6 +83,7 @@ write_hdl -pg > $::env(SOCLABS_PROJECT_DIR)/imp/ASIC/nanosoc/netlist/nanosoc_chi
write_sdf -timescale ns > $::env(SOCLABS_PROJECT_DIR)/imp/ASIC/nanosoc/netlist/nanosoc_chip_pads_44pin.sdf
write_do_lec -revised_design $::env(SOCLABS_PROJECT_DIR)/imp/ASIC/nanosoc/netlist/nanosoc_chip_pads_44pin.v -no_lp -top nanosoc_chip_pads -logfile $::env(SOCLABS_PROJECT_DIR)/imp/ASIC/nanosoc/ > lec.dofile
#report_scan_chains > $::env(SOCLABS_PROJECT_DIR)/imp/ASIC/nanosoc/dft/nanosoc_scan_chains_44pin.rep
#report_scan_setup > $::env(SOCLABS_PROJECT_DIR)/imp/ASIC/nanosoc/dft/nanosoc_scan_setup_44pin.rep
#report_scan_registers > $::env(SOCLABS_PROJECT_DIR)/imp/ASIC/nanosoc/dft/nanosoc_scan_registers_44pin.rep
......
ASIC/44pin/Cadence/scripts/io_plan.tcl
+ 2
− 2
View file @ 43092cb3
......@@ -22,8 +22,8 @@ delete_io_fillers -cell PFILLER0005
read_io_file nanosoc_io_plan.io
add_io_fillers -cells PCORNER -prefix CORNER -side n -from -300 -to 300
add_io_fillers -cells PCORNER -prefix CORNER -side e -from 500 -to 3000
add_io_fillers -cells PCORNER -prefix CORNER -side s -from 500 -to 3000
add_io_fillers -cells PCORNER -prefix CORNER -side e -from 1380 -to 3000
add_io_fillers -cells PCORNER -prefix CORNER -side s -from 880 -to 2000
add_io_fillers -cells PCORNER -prefix CORNER -side w -from -300 -to 300
add_io_fillers -cells PFILLER20 -prefix FILLER -side n
......
ASIC/44pin/Cadence/scripts/nanosoc_io_plan.io
+ 24
− 30
View file @ 43092cb3
......@@ -21,21 +21,18 @@
(inst name="uPAD_P1_01" offset=800.71 place_status=placed )
)
(left
(inst name="uPAD_P0_04" offset=153.67 place_status=placed )
(inst name="uPAD_P0_05" offset=271.00 place_status=placed )
(inst name="RESERVED " offset=388.33 place_status=placed )
(inst name="RESERVED " offset=505.67 place_status=placed )
(inst name="uPAD_P0_03" offset=149.29 place_status=placed )
(inst name="uPAD_VDDACC_0" offset=257.86 place_status=placed )
(inst name="uPAD_VSS_0" offset=366.43 place_status=placed )
(inst name="uPAD_CLK_I" offset=475.00 place_status=placed )
(inst name="uPAD_VDD_0" offset=583.57 place_status=placed )
(inst name="uPAD_VDDIO_0" offset=692.14 place_status=placed )
(inst name="uPAD_SWDIO_IO" offset=800.71 place_status=placed )
(inst name="uPAD_VSSIO_0" offset=1444.33 place_status=placed )
(inst name="RESERVED " offset=1561.67 place_status=placed )
(inst name="uPAD_P0_06" offset=1679.00 place_status=placed )
(inst name="uPAD_P0_07" offset=1796.33 place_status=placed )
(inst name="uPAD_P0_04" offset=146.25 place_status=placed )
(inst name="uPAD_P0_05" offset=251.25 place_status=placed )
(inst name="uPAD_P0_03" offset=356.25 place_status=placed )
(inst name="uPAD_VDDACC_0" offset=461.25 place_status=placed )
(inst name="uPAD_VSS_0" offset=566.25 place_status=placed )
(inst name="uPAD_CLK_I" offset=671.25 place_status=placed )
(inst name="uPAD_VDD_0" offset=776.25 place_status=placed )
(inst name="uPAD_VDDIO_0" offset=881.25 place_status=placed )
(inst name="uPAD_SWDIO_IO" offset=986.25 place_status=placed )
(inst name="uPAD_VSSIO_0" offset=1091.25 place_status=placed )
(inst name="uPAD_P0_06" offset=1196.25 place_status=placed )
(inst name="uPAD_P0_07" offset=1301.25 place_status=placed )
)
(bottom
(inst name="uPAD_P0_02" offset=149.29 place_status=placed )
......@@ -47,20 +44,17 @@
(inst name="uPAD_P0_00" offset=800.71 )
)
(right
(inst name="uPAD_P1_07" offset=153.67 place_status=placed )
(inst name="uPAD_P1_06" offset=271.00 place_status=placed )
(inst name="RESERVED " offset=388.33 place_status=placed )
(inst name="uPAD_VSSIO_1" offset=505.67 place_status=placed )
(inst name="uPAD_P1_03" offset=149.29 place_status=placed )
(inst name="uPAD_P1_02" offset=257.86 place_status=placed )
(inst name="uPAD_VDDACC_2" offset=366.43 place_status=placed )
(inst name="uPAD_VDD_2" offset=475.00 place_status=placed )
(inst name="uPAD_VSS_2" offset=583.57 place_status=placed )
(inst name="uPAD_VDDIO_2" offset=692.14 place_status=placed )
(inst name="uPAD_NRST_I" offset=800.71 place_status=placed )
(inst name="RESERVED " offset=1444.33 place_status=placed )
(inst name="RESERVED " offset=1561.67 place_status=placed )
(inst name="uPAD_P1_04" offset=1679.00 place_status=placed )
(inst name="uPAD_P1_05" offset=1796.33 place_status=placed )
(inst name="uPAD_P1_07" offset=146.25 place_status=placed )
(inst name="uPAD_P1_06" offset=251.25 place_status=placed )
(inst name="uPAD_VSSIO_1" offset=356.25 place_status=placed )
(inst name="uPAD_P1_03" offset=461.25 place_status=placed )
(inst name="uPAD_P1_02" offset=566.25 place_status=placed )
(inst name="uPAD_VDDACC_2" offset=671.25 place_status=placed )
(inst name="uPAD_VDD_2" offset=776.25 place_status=placed )
(inst name="uPAD_VSS_2" offset=881.25 place_status=placed )
(inst name="uPAD_VDDIO_2" offset=986.25 place_status=placed )
(inst name="uPAD_NRST_I" offset=1091.25 place_status=placed )
(inst name="uPAD_P1_04" offset=1196.25 place_status=placed )
(inst name="uPAD_P1_05" offset=1301.25 place_status=placed )
)
)
ASIC/44pin/Cadence/scripts/place.tcl
+ 1
− 1
View file @ 43092cb3
......@@ -15,7 +15,7 @@ set_db place_global_uniform_density true
### Placement Mode Config
set_db place_design_floorplan_mode false
place_opt_design
place_design
### Delay Calculation
write_sdf design.sdf -ideal_clock_network
ASIC/44pin/Cadence/scripts/place_macros.tcl
+ 4
− 1
View file @ 43092cb3
......@@ -9,6 +9,7 @@
#------------------------------------------------------------------------------------
# relative floorplan
gui_set_draw_view fplan
delete_relative_floorplan -all
create_relative_floorplan -ref_type core_boundary -horizontal_edge_separate {1 -4.8 1} -vertical_edge_separate {2 -2.4 2} -place u_nanosoc_chip_u_system_u_ss_expansion_u_region_expram_l_u_expram_l_u_sram_genblk1.u_rf_sp_hdf
create_relative_floorplan -ref_type object -horizontal_edge_separate {3 -12 1} -vertical_edge_separate {3 0 3} -place u_nanosoc_chip_u_system_u_ss_expansion_u_region_expram_h_u_expram_h_u_sram_genblk1.u_rf_sp_hdf -ref u_nanosoc_chip_u_system_u_ss_expansion_u_region_expram_l_u_expram_l_u_sram_genblk1.u_rf_sp_hdf
......@@ -18,7 +19,7 @@ create_relative_floorplan -ref_type core_boundary -orient R0 -horizontal_edge_se
move_obj u_nanosoc_chip_u_system_u_ss_expansion_u_region_exp_u_ss_accelerator -point {500 500}
update_floorplan_obj -obj u_nanosoc_chip_u_system_u_ss_expansion_u_region_exp_u_ss_accelerator -rects {150 150 500 351.6}
add_fences -hinst u_nanosoc_chip_u_system_u_ss_expansion_u_region_exp_u_ss_accelerator -min_gap 5
add_fences -hinst u_nanosoc_chip_u_system_u_ss_expansion_u_region_exp_u_ss_accelerator -min_gap 2.4
create_partition -hinst u_nanosoc_chip_u_system_u_ss_expansion_u_region_exp_u_ss_accelerator -core_spacing 2.0 2.0 2.0 2.0 -rail_width 0.0 -min_pitch_left 2 -min_pitch_right 2 -min_pitch_top 2 -min_pitch_bottom 2 -reserved_layer { 1 2 3 4 5 6 7 8 9 10} -pin_layer_top { 2 4 6 8 10} -pin_layer_left { 3 5 7 9} -pin_layer_bottom { 2 4 6 8 10} -pin_layer_right { 3 5 7 9} -place_halo 2 2 2 2 -route_halo 2.0 -route_halo_top_layer 5 -route_halo_bottom_layer 1
create_place_halo -halo_deltas {4.8 4.8 2.4 4.8} -insts u_nanosoc_chip_u_system_u_ss_expansion_u_region_expram_l_u_expram_l_u_sram_genblk1.u_rf_sp_hdf
......@@ -26,3 +27,5 @@ create_place_halo -halo_deltas {4.8 4.8 2.4 4.8} -insts u_nanosoc_chip_u_system_
create_place_halo -halo_deltas {4.8 4.8 2.4 4.8} -insts u_nanosoc_chip_u_system_u_ss_cpu_u_region_imem_0_u_imem_0_u_sram_genblk1.u_rf_sp_hdf
create_place_halo -halo_deltas {4.8 4.8 2.4 4.8} -insts u_nanosoc_chip_u_system_u_ss_cpu_u_region_dmem_0_u_dmem_0_u_sram_genblk1.u_rf_sp_hdf
create_place_halo -halo_deltas {4.8 4.8 2.4 4.8} -insts u_nanosoc_chip_u_system_u_ss_cpu_u_region_bootrom_0_u_bootrom_cpu_0_u_bootrom_u_sl_rom
add_fences -hinst u_nanosoc_chip_u_system_u_ss_expansion_u_region_exp_u_ss_accelerator -min_gap 2.4
\ No newline at end of file
ASIC/constraints.sdc
+ 3
− 3
View file @ 43092cb3
......@@ -22,9 +22,9 @@ set SWDCLK_PERIOD 20;
create_clock -name "$EXTCLK" -period "$EXTCLK_PERIOD" -waveform "0 [expr $EXTCLK_PERIOD/2]" [get_ports CLK]
create_clock -name "$SWDCLK" -period "$SWDCLK_PERIOD" -waveform "0 [expr $SWDCLK_PERIOD/2]" [get_ports SWDCK]
set SKEW 0.200
set_clock_uncertainty $SKEW [get_clocks $EXTCLK]
set_clock_uncertainty $SKEW [get_clocks $SWDCLK]
set SKEW 0.800
set_clock_uncertainty [expr 0.15*$EXTCLK_PERIOD] [get_clocks $EXTCLK]
set_clock_uncertainty [expr 0.15*$SWDCLK_PERIOD] [get_clocks $SWDCLK]
set MINRISE 0.20
set MAXRISE 0.25
......
ASIC/nanosoc_chip_pads/tsmc65lp/nanosoc_chip_pads_44pin.v
+ 255
− 151
View file @ 43092cb3
......@@ -35,7 +35,6 @@
// Abstract : Top level for example Cortex-M0/Cortex-M0+ microcontroller
//-----------------------------------------------------------------------------
//
`define POWER_PINS
module nanosoc_chip_pads (
inout wire VDDIO,
inout wire VSSIO,
......@@ -55,27 +54,123 @@ module nanosoc_chip_pads (
//------------------------------------
// internal wires
wire clk_i;
wire test_i;
wire nrst_i;
wire [15:0] p0_i; // level-shifted input from pad
wire [15:0] p0_o; // output port drive
wire [15:0] p0_e; // active high output drive enable (pad tech dependent)
wire [15:0] p0_z; // active low output drive enable (pad tech dependent)
wire [15:0] p1_i; // level-shifted input from pad
wire [15:0] p1_o; // output port drive
wire [15:0] p1_e; // active high output drive enable (pad tech dependent)
wire [15:0] p1_z; // active low output drive enable (pad tech dependent)
wire swdio_i;
wire swdio_o;
wire swdio_e;
wire swdio_z;
wire swdclk_i;
// --------------------------------------------------------------------------------
// Cortex-M0 nanosoc Microcontroller
// --------------------------------------------------------------------------------
localparam GPIO_TIO = 4;
wire pad_clk_i;
wire pad_nrst_i;
wire pad_test_i;
wire pad_swdclk_i;
wire pad_swdio_i;
wire pad_swdio_o;
wire pad_swdio_e;
wire pad_swdio_z;
wire [15:0] pad_gpio_port0_i ;
wire [15:0] pad_gpio_port0_o ;
wire [15:0] pad_gpio_port0_e ;
wire [15:0] pad_gpio_port0_z ;
wire [15:0] pad_gpio_port1_i ;
wire [15:0] pad_gpio_port1_o ;
wire [15:0] pad_gpio_port1_e ;
wire [15:0] pad_gpio_port1_z ;
wire soc_nreset;
wire soc_diag_mode;
wire soc_diag_ctrl;
wire soc_scan_mode;
wire soc_scan_enable;
wire [GPIO_TIO-1:0] soc_scan_in; //soc test status outputs
wire [GPIO_TIO-1:0] soc_scan_out; //soc test status outputs
wire soc_bist_mode;
wire soc_bist_enable;
wire [GPIO_TIO-1:0] soc_bist_in; //soc test status outputs
wire [GPIO_TIO-1:0] soc_bist_out; //soc test status outputs
wire soc_alt_mode; // ALT MODE = UART
wire soc_uart_rxd_i; // UART RXD
wire soc_uart_txd_o = 1'b1; // UART TXD
wire soc_swd_mode; // SWD mode
wire soc_swd_clk_i; // SWDCLK
wire soc_swd_dio_i; // SWDIO tristate input
wire soc_swd_dio_o; // SWDIO trstate output
wire soc_swd_dio_e; // SWDIO tristate output enable
wire soc_swd_dio_z; // SWDIO tristate output hiz
wire [15:0] soc_gpio_port0_i; // GPIO SOC tristate input
wire [15:0] soc_gpio_port0_o; // GPIO SOC trstate output
wire [15:0] soc_gpio_port0_e; // GPIO SOC tristate output enable
wire [15:0] soc_gpio_port0_z; // GPIO SOC tristate output hiz
wire [15:0] soc_gpio_port1_i; // GPIO SOC tristate input
wire [15:0] soc_gpio_port1_o; // GPIO SOC trstate output
wire [15:0] soc_gpio_port1_e; // GPIO SOC tristate output enable
wire [15:0] soc_gpio_port1_z; // GPIO SOC tristate output hiz
// connect up high order GPIOs
assign soc_gpio_port0_i[15:GPIO_TIO] = pad_gpio_port0_i[15:GPIO_TIO];
assign pad_gpio_port0_o[15:GPIO_TIO] = soc_gpio_port0_o[15:GPIO_TIO];
assign pad_gpio_port0_e[15:GPIO_TIO] = soc_gpio_port0_e[15:GPIO_TIO];
assign pad_gpio_port0_z[15:GPIO_TIO] = soc_gpio_port0_z[15:GPIO_TIO];
assign soc_gpio_port1_i[15:GPIO_TIO] = pad_gpio_port1_i[15:GPIO_TIO];
assign pad_gpio_port1_o[15:GPIO_TIO] = soc_gpio_port1_o[15:GPIO_TIO];
assign pad_gpio_port1_e[15:GPIO_TIO] = soc_gpio_port1_e[15:GPIO_TIO];
assign pad_gpio_port1_z[15:GPIO_TIO] = soc_gpio_port1_z[15:GPIO_TIO];
wire tiehi = 1'b1;
wire tielo = 1'b0;
nanosoc_chip_cfg #(
.GPIO_TIO (GPIO_TIO)
)
u_nanosoc_chip_cfg
(
// Primary Inputs
.pad_clk_i (pad_clk_i )
,.pad_nrst_i (pad_nrst_i )
,.pad_test_i (pad_test_i )
// Alternate/reconfigurable IP and associated bidirectional I/O
,.pad_altin_i (pad_swdclk_i ) // SWCLK/UARTRXD/SCAN-ENABLE
,.pad_altio_i (pad_swdio_i ) // SWDIO/UARTTXD tristate input
,.pad_altio_o (pad_swdio_o ) // SWDIO/UARTTXD trstate output
,.pad_altio_e (pad_swdio_e ) // SWDIO/UARTTXD tristate output enable
,.pad_altio_z (pad_swdio_z ) // SWDIO/UARTTXD tristate output hiz
// Reconfigurable General Purpose bidirectional I/Os Port-0 (user)
,.pad_gpio_port0_i (pad_gpio_port0_i[GPIO_TIO-1:0]) // GPIO PAD tristate input
,.pad_gpio_port0_o (pad_gpio_port0_o[GPIO_TIO-1:0]) // GPIO PAD trstate output
,.pad_gpio_port0_e (pad_gpio_port0_e[GPIO_TIO-1:0]) // GPIO PAD tristate output enable
,.pad_gpio_port0_z (pad_gpio_port0_z[GPIO_TIO-1:0]) // GPIO PAD tristate output hiz
// Reconfigurable General Purpose bidirectional I/Os Port-1 (system)
,.pad_gpio_port1_i (pad_gpio_port1_i[GPIO_TIO-1:0]) // GPIO PAD tristate input
,.pad_gpio_port1_o (pad_gpio_port1_o[GPIO_TIO-1:0]) // GPIO PAD trstate output
,.pad_gpio_port1_e (pad_gpio_port1_e[GPIO_TIO-1:0]) // GPIO PAD tristate output enable
,.pad_gpio_port1_z (pad_gpio_port1_z[GPIO_TIO-1:0]) // GPIO PAD tristate output hiz
//SOC
,.soc_nreset (soc_nreset )
,.soc_diag_mode (soc_diag_mode )
,.soc_diag_ctrl (soc_diag_ctrl )
,.soc_scan_mode (soc_scan_mode )
,.soc_scan_enable (soc_scan_enable )
,.soc_scan_in (soc_scan_in ) // soc test scan chain inputs
,.soc_scan_out (soc_scan_out ) // soc test scan chain outputs
,.soc_bist_mode (soc_bist_mode )
,.soc_bist_enable (soc_bist_enable )
,.soc_bist_in (soc_bist_in ) // soc bist control inputs
,.soc_bist_out (soc_bist_out ) // soc test status outputs
,.soc_alt_mode (soc_alt_mode )// ALT MODE = UART
,.soc_uart_rxd_i (soc_uart_rxd_i ) // UART RXD
,.soc_uart_txd_o (soc_uart_txd_o ) // UART TXD
,.soc_swd_mode (soc_swd_mode ) // SWD mode
,.soc_swd_clk_i (soc_swd_clk_i ) // SWDCLK
,.soc_swd_dio_i (soc_swd_dio_i ) // SWDIO tristate input
,.soc_swd_dio_o (soc_swd_dio_o ) // SWDIO trstate output
,.soc_swd_dio_e (soc_swd_dio_e ) // SWDIO tristate output enable
,.soc_swd_dio_z (soc_swd_dio_z ) // SWDIO tristate output hiz
,.soc_gpio_port0_i (soc_gpio_port0_i[GPIO_TIO-1:0]) // GPIO SOC tristate input
,.soc_gpio_port0_o (soc_gpio_port0_o[GPIO_TIO-1:0]) // GPIO SOC trstate output
,.soc_gpio_port0_e (soc_gpio_port0_e[GPIO_TIO-1:0]) // GPIO SOC tristate output enable
,.soc_gpio_port0_z (soc_gpio_port0_z[GPIO_TIO-1:0]) // GPIO SOC tristate output hiz
,.soc_gpio_port1_i (soc_gpio_port1_i[GPIO_TIO-1:0]) // GPIO SOC tristate input
,.soc_gpio_port1_o (soc_gpio_port1_o[GPIO_TIO-1:0]) // GPIO SOC trstate output
,.soc_gpio_port1_e (soc_gpio_port1_e[GPIO_TIO-1:0]) // GPIO SOC tristate output enable
,.soc_gpio_port1_z (soc_gpio_port1_z[GPIO_TIO-1:0]) // GPIO SOC tristate output hiz
);
nanosoc_chip u_nanosoc_chip (
`ifdef POWER_PINS
......@@ -83,34 +178,43 @@ module nanosoc_chip_pads (
.VSS (VSS),
.VDDACC (VDDACC),
`endif
.clk_i(clk_i),
.test_i(test_i),
.nrst_i(nrst_i),
.p0_i(p0_i), // level-shifted input from pad
.p0_o(p0_o), // output port drive
.p0_e(p0_e), // active high output drive enable (pad tech dependent)
.p0_z(p0_z), // active low output drive enable (pad tech dependent)
.p1_i(p1_i), // level-shifted input from pad
.p1_o(p1_o), // output port drive
.p1_e(p1_e), // active high output drive enable (pad tech dependent)
.p1_z(p1_z), // active low output drive enable (pad tech dependent)
.swdio_i(swdio_i),
.swdio_o(swdio_o),
.swdio_e(swdio_e),
.swdio_z(swdio_z),
.swdclk_i(swdclk_i)
`ifdef ASIC_TEST_PORTS
.diag_mode (soc_diag_mode ),
.diag_ctrl (soc_diag_ctrl ),
.scan_mode (soc_scan_mode ),
.scan_enable (soc_scan_enable ),
.scan_in (soc_scan_in ), // soc test scan chain inputs
.scan_out (soc_scan_out ), // soc test scan chain outputs
.bist_mode (soc_bist_mode ),
.bist_enable (soc_bist_enable ),
.bist_in (soc_bist_in ), // soc bist control inputs
.bist_out (soc_bist_out ), // soc test status outputs
.alt_mode (soc_alt_mode )// ALT MODE = UART
.uart_rxd_i (soc_uart_rxd_i ) // UART RXD
.uart_txd_o (soc_uart_txd_o ) // UART TXD
.swd_mode (soc_swd_mode ), // SWD mode
`endif
.clk_i(pad_clk_i),
.test_i(soc_scan_mode),
.nrst_i(soc_nreset),
.p0_i(soc_gpio_port0_i), // level-shifted input from pad
.p0_o(soc_gpio_port0_o), // output port drive
.p0_e(soc_gpio_port0_e), // active high output drive enable (pad tech dependent)
.p0_z(soc_gpio_port0_z), // active low output drive enable (pad tech dependent)
.p1_i(soc_gpio_port1_i), // level-shifted input from pad
.p1_o(soc_gpio_port1_o), // output port drive
.p1_e(soc_gpio_port1_e), // active high output drive enable (pad tech dependent)
.p1_z(soc_gpio_port1_z), // active low output drive enable (pad tech dependent)
.swdio_i(soc_swd_dio_i),
.swdio_o(soc_swd_dio_o),
.swdio_e(soc_swd_dio_e),
.swdio_z(soc_swd_dio_z),
.swdclk_i(soc_swd_clk_i)
);
//TIE_HI uTIEHI (.tiehi(tiehi));
wire tiehi = 1'b1;
//TIE_LO uTIELO (.tielo(tielo));
wire tielo = 1'b0;
wire dft_sdi_1, dft_sdi_2, dft_sdo_1, dft_sdo_2;
// --------------------------------------------------------------------------------
// IO pad (GLIB Generic Library napping)
// IO pad (TSMC 65nm specific Library napping)
// --------------------------------------------------------------------------------
// Pad IO power supplies
......@@ -177,7 +281,7 @@ PVDD1CDG uPAD_VDDACC_2(
PRDW0408SCDG uPAD_CLK_I (
.IE(tiehi),
.C(clk_i),
.C(pad_clk_i),
.PE(tielo),
.DS(tielo),
.I(tielo),
......@@ -187,7 +291,7 @@ PRDW0408SCDG uPAD_CLK_I (
PRDW0408SCDG uPAD_TEST_I (
.IE(tiehi),
.C(test_i),
.C(pad_test_i),
.PE(tielo),
.DS(tielo),
.I(tielo),
......@@ -197,7 +301,7 @@ PRDW0408SCDG uPAD_TEST_I (
PRDW0408SCDG uPAD_NRST_I (
.IE(tiehi),
.C(nrst_i),
.C(pad_nrst_i),
.PE(tielo),
.DS(tielo),
.I(tielo),
......@@ -206,18 +310,18 @@ PRDW0408SCDG uPAD_NRST_I (
);
PRDW0408SCDG uPAD_SWDIO_IO (
.IE(swdio_z),
.C(swdio_i),
.IE(pad_swdio_z),
.C(pad_swdio_i),
.PE(tielo),
.DS(tielo),
.I(swdio_o),
.OEN(swdio_z),
.I(pad_swdio_o),
.OEN(pad_swdio_z),
.PAD(SWDIO)
);
PRDW0408SCDG uPAD_SWDCK_I (
.IE(tiehi),
.C(swdclk_i),
.C(pad_swdclk_i),
.PE(tielo),
.DS(tielo),
.I(tielo),
......@@ -228,184 +332,184 @@ PRDW0408SCDG uPAD_SWDCK_I (
// GPI.I Port 0 x 16
PRDW0408SCDG uPAD_P0_00 (
.IE(p0_z[00]),
.C(p0_i[00]),
.PE(p0_z[00]&p0_o[00]),
.IE(pad_gpio_port0_z[00]),
.C(pad_gpio_port0_i[00]),
.PE(pad_gpio_port0_z[00]&pad_gpio_port0_o[00]),
.DS(tielo),
.I(p0_o[00]),
.OEN(p0_z[00]),
.I(pad_gpio_port0_o[00]),
.OEN(pad_gpio_port0_z[00]),
.PAD(P0[00])
);
PRDW0408SCDG uPAD_P0_01 (
.IE(p0_z[01]),
.C(p0_i[01]),
.PE(p0_z[01]&p0_o[01]),
.IE(pad_gpio_port0_z[01]),
.C(pad_gpio_port0_i[01]),
.PE(pad_gpio_port0_z[01]&pad_gpio_port0_o[01]),
.DS(tielo),
.I(p0_o[01]),
.OEN(p0_z[01]),
.I(pad_gpio_port0_o[01]),
.OEN(pad_gpio_port0_z[01]),
.PAD(P0[01])
);
PRDW0408SCDG uPAD_P0_02 (
.IE(p0_z[02]),
.C(p0_i[02]),
.PE(p0_z[02]&p0_o[02]),
.IE(pad_gpio_port0_z[02]),
.C(pad_gpio_port0_i[02]),
.PE(pad_gpio_port0_z[02]&pad_gpio_port0_o[02]),
.DS(tielo),
.I(p0_o[02]),
.OEN(p0_z[02]),
.I(pad_gpio_port0_o[02]),
.OEN(pad_gpio_port0_z[02]),
.PAD(P0[02])
);
PRDW0408SCDG uPAD_P0_03 (
.IE(p0_z[03]),
.C(p0_i[03]),
.PE(p0_z[03]&p0_o[03]),
.IE(pad_gpio_port0_z[03]),
.C(pad_gpio_port0_i[03]),
.PE(pad_gpio_port0_z[03]&pad_gpio_port0_o[03]),
.DS(tielo),
.I(p0_o[03]),
.OEN(p0_z[03]),
.I(pad_gpio_port0_o[03]),
.OEN(pad_gpio_port0_z[03]),
.PAD(P0[03])
);
PRDW0408SCDG uPAD_P0_04 (
.IE(p0_z[04]),
.C(p0_i[04]),
.PE(p0_z[04]&p0_o[04]),
.IE(pad_gpio_port0_z[04]),
.C(pad_gpio_port0_i[04]),
.PE(pad_gpio_port0_z[04]&pad_gpio_port0_o[04]),
.DS(tielo),
.I(p0_o[04]),
.OEN(p0_z[04]),
.I(pad_gpio_port0_o[04]),
.OEN(pad_gpio_port0_z[04]),
.PAD(P0[04])
);
PRDW0408SCDG uPAD_P0_05 (
.IE(p0_z[05]),
.C(p0_i[05]),
.PE(p0_z[05]&p0_o[05]),
.IE(pad_gpio_port0_z[05]),
.C(pad_gpio_port0_i[05]),
.PE(pad_gpio_port0_z[05]&pad_gpio_port0_o[05]),
.DS(tielo),
.I(p0_o[05]),
.OEN(p0_z[05]),
.I(pad_gpio_port0_o[05]),
.OEN(pad_gpio_port0_z[05]),
.PAD(P0[05])
);
PRDW0408SCDG uPAD_P0_06 (
.IE(p0_z[06]),
.C(p0_i[06]),
.PE(p0_z[06]&p0_o[06]),
.IE(pad_gpio_port0_z[06]),
.C(pad_gpio_port0_i[06]),
.PE(pad_gpio_port0_z[06]&pad_gpio_port0_o[06]),
.DS(tielo),
.I(p0_o[06]),
.OEN(p0_z[06]),
.I(pad_gpio_port0_o[06]),
.OEN(pad_gpio_port0_z[06]),
.PAD(P0[06])
);
PRDW0408SCDG uPAD_P0_07 (
.IE(p0_z[07]),
.C(p0_i[07]),
.PE(p0_z[07]&p0_o[07]),
.IE(pad_gpio_port0_z[07]),
.C(pad_gpio_port0_i[07]),
.PE(pad_gpio_port0_z[07]&pad_gpio_port0_o[07]),
.DS(tielo),
.I(p0_o[07]),
.OEN(p0_z[07]),
.I(pad_gpio_port0_o[07]),
.OEN(pad_gpio_port0_z[07]),
.PAD(P0[07])
);
// GPI.I Port 1 x 16
PRDW0408SCDG uPAD_P1_00 (
.IE(p1_z[00]),
.C(p1_i[00]),
.PE(p1_z[00]&p1_o[00]),
.IE(pad_gpio_port1_z[00]),
.C(pad_gpio_port1_i[00]),
.PE(pad_gpio_port1_z[00]&pad_gpio_port1_o[00]),
.DS(tielo),
.I(p1_o[00]),
.OEN(p1_z[00]),
.I(pad_gpio_port1_o[00]),
.OEN(pad_gpio_port1_z[00]),
.PAD(P1[00])
);
PRDW0408SCDG uPAD_P1_01 (
.IE(p1_z[01]),
.C(p1_i[01]),
.PE(p1_z[01]&p1_o[01]),
.IE(pad_gpio_port1_z[01]),
.C(pad_gpio_port1_i[01]),
.PE(pad_gpio_port1_z[01]&pad_gpio_port1_o[01]),
.DS(tielo),
.I(p1_o[01]),
.OEN(p1_z[01]),
.I(pad_gpio_port1_o[01]),
.OEN(pad_gpio_port1_z[01]),
.PAD(P1[01])
);
PRDW0408SCDG uPAD_P1_02 (
.IE(p1_z[02]),
.C(p1_i[02]),
.PE(p1_z[02]&p1_o[02]),
.IE(pad_gpio_port1_z[02]),
.C(pad_gpio_port1_i[02]),
.PE(pad_gpio_port1_z[02]&pad_gpio_port1_o[02]),
.DS(tielo),
.I(p1_o[02]),
.OEN(p1_z[02]),
.I(pad_gpio_port1_o[02]),
.OEN(pad_gpio_port1_z[02]),
.PAD(P1[02])
);
PRDW0408SCDG uPAD_P1_03 (
.IE(p1_z[03]),
.C(p1_i[03]),
.PE(p1_z[03]&p1_o[03]),
.IE(pad_gpio_port1_z[03]),
.C(pad_gpio_port1_i[03]),
.PE(pad_gpio_port1_z[03]&pad_gpio_port1_o[03]),
.DS(tielo),
.I(p1_o[03]),
.OEN(p1_z[03]),
.I(pad_gpio_port1_o[03]),
.OEN(pad_gpio_port1_z[03]),
.PAD(P1[03])
);
PRDW0408SCDG uPAD_P1_04 (
.IE(p1_z[04]),
.C(p1_i[04]),
.PE(p1_z[04]&p1_o[04]),
.IE(pad_gpio_port1_z[04]),
.C(pad_gpio_port1_i[04]),
.PE(pad_gpio_port1_z[04]&pad_gpio_port1_o[04]),
.DS(tielo),
.I(p1_o[04]),
.OEN(p1_z[04]),
.I(pad_gpio_port1_o[04]),
.OEN(pad_gpio_port1_z[04]),
.PAD(P1[04])
);
PRDW0408SCDG uPAD_P1_05 (
.IE(p1_z[05]),
.C(p1_i[05]),
.PE(p1_z[05]&p1_o[05]),
.IE(pad_gpio_port1_z[05]),
.C(pad_gpio_port1_i[05]),
.PE(pad_gpio_port1_z[05]&pad_gpio_port1_o[05]),
.DS(tielo),
.I(p1_o[05]),
.OEN(p1_z[05]),
.I(pad_gpio_port1_o[05]),
.OEN(pad_gpio_port1_z[05]),
.PAD(P1[05])
);
PRDW0408SCDG uPAD_P1_06 (
.IE(p1_z[06]),
.C(p1_i[06]),
.PE(p1_z[06]&p1_o[06]),
.IE(pad_gpio_port1_z[06]),
.C(pad_gpio_port1_i[06]),
.PE(pad_gpio_port1_z[06]&pad_gpio_port1_o[06]),
.DS(tielo),
.I(p1_o[06]),
.OEN(p1_z[06]),
.I(pad_gpio_port1_o[06]),
.OEN(pad_gpio_port1_z[06]),
.PAD(P1[06])
);
PRDW0408SCDG uPAD_P1_07 (
.IE(p1_z[07]),
.C(p1_i[07]),
.PE(p1_z[07]&p1_o[07]),
.IE(pad_gpio_port1_z[07]),
.C(pad_gpio_port1_i[07]),
.PE(pad_gpio_port1_z[07]&pad_gpio_port1_o[07]),
.DS(tielo),
.I(p1_o[07]),
.OEN(p1_z[07]),
.I(pad_gpio_port1_o[07]),
.OEN(pad_gpio_port1_z[07]),
.PAD(P1[07])
);
assign p0_i[8] = p0_o[8] & p0_e[8];
assign p0_i[9] = p0_o[9] & p0_e[9];
assign p0_i[10] = p0_o[10] & p0_e[10];
assign p0_i[11] = p0_o[11] & p0_e[11];
assign p0_i[12] = p0_o[12] & p0_e[12];
assign p0_i[13] = p0_o[13] & p0_e[13];
assign p0_i[14] = p0_o[14] & p0_e[14];
assign p0_i[15] = p0_o[15] & p0_e[15];
assign p1_i[8] = p1_o[8] & p1_e[8];
assign p1_i[9] = p1_o[9] & p1_e[9];
assign p1_i[10] = p1_o[10] & p1_e[10];
assign p1_i[11] = p1_o[11] & p1_e[11];
assign p1_i[12] = p1_o[12] & p1_e[12];
assign p1_i[13] = p1_o[13] & p1_e[13];
assign p1_i[14] = p1_o[14] & p1_e[14];
assign p1_i[15] = p1_o[15] & p1_e[15];
assign pad_gpio_port0_i[8] = pad_gpio_port0_o[8] & pad_gpio_port0_e[8];
assign pad_gpio_port0_i[9] = pad_gpio_port0_o[9] & pad_gpio_port0_e[9];
assign pad_gpio_port0_i[10] = pad_gpio_port0_o[10] & pad_gpio_port0_e[10];
assign pad_gpio_port0_i[11] = pad_gpio_port0_o[11] & pad_gpio_port0_e[11];
assign pad_gpio_port0_i[12] = pad_gpio_port0_o[12] & pad_gpio_port0_e[12];
assign pad_gpio_port0_i[13] = pad_gpio_port0_o[13] & pad_gpio_port0_e[13];
assign pad_gpio_port0_i[14] = pad_gpio_port0_o[14] & pad_gpio_port0_e[14];
assign pad_gpio_port0_i[15] = pad_gpio_port0_o[15] & pad_gpio_port0_e[15];
assign pad_gpio_port1_i[8] = pad_gpio_port1_o[8] & pad_gpio_port1_e[8];
assign pad_gpio_port1_i[9] = pad_gpio_port1_o[9] & pad_gpio_port1_e[9];
assign pad_gpio_port1_i[10] = pad_gpio_port1_o[10] & pad_gpio_port1_e[10];
assign pad_gpio_port1_i[11] = pad_gpio_port1_o[11] & pad_gpio_port1_e[11];
assign pad_gpio_port1_i[12] = pad_gpio_port1_o[12] & pad_gpio_port1_e[12];
assign pad_gpio_port1_i[13] = pad_gpio_port1_o[13] & pad_gpio_port1_e[13];
assign pad_gpio_port1_i[14] = pad_gpio_port1_o[14] & pad_gpio_port1_e[14];
assign pad_gpio_port1_i[15] = pad_gpio_port1_o[15] & pad_gpio_port1_e[15];
endmodule
......
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