Updated lint flow and updated vsim flow

hal/corstone101_ip.bb

@@ -62,6 +62,10 @@ bb_list
     designunit = cmsdk_apb_slave_mux;
     file = $ARM_IP_LIBRARY_PATH/latest/Corstone-101/logical/cmsdk_apb_slave_mux/verilog/cmsdk_apb_slave_mux.v;
     
+    // Exclude CMSDK FPGA ROM
+    designunit = cmsdk_fpga_rom;
+    file = $ARM_IP_LIBRARY_PATH/latest/Corstone-101/logical/models/memories/cmsdk_fpga_rom.v;
+    
     // Exclude APB Test slave as Arm IP
     designunit = cmsdk_apb_test_slave;
     file = $ARM_IP_LIBRARY_PATH/latest/Corstone-101/logical/cmsdk_apb_subsystem/verilog/cmsdk_apb_test_slave.v;

makefile

@@ -123,8 +123,8 @@ LINT_INFO_SOCDEBUG_DIR = $(SOCLABS_SOCDEBUG_TECH_DIR)/hal
 LINT_TOP = nanosoc_chip_pads
 
 # MTI option
-#DF#MTI_OPTIONS    = -novopt
-MTI_OPTIONS    = -suppress 2892
+MTI_OPTIONS    = +acc
+MTI_OPTIONS    += -suppress 2892
 MTI_VC_OPTIONS = -f $(TBENCH_VC) $(ACCELERATOR_VC) $(ADP_OPTIONS)
 
 # VCS option
@@ -211,7 +211,7 @@ compile_xm : bootrom
 lint_xm: bootrom
 	@rm -rf $(LINT_DIR) 
 	@mkdir -p $(LINT_DIR)
-	cd $(LINT_DIR); hal -f $(DESIGN_VC) $(DEFINES_VC) +debug -XMVERILOGARGS "-timescale 1ps/1ps" -top $(LINT_TOP) $(HAL_BLACK_BOX) $(HAL_WAIVE) $(LINT_NOCHECK)
+	cd $(LINT_DIR); xrun -hal -f $(DESIGN_VC) $(DEFINES_VC) +debug "-timescale 1ps/1ps" -top $(LINT_TOP) $(HAL_BLACK_BOX) $(HAL_WAIVE) $(LINT_NOCHECK)
 	
 # Note : If coverage is required, you can add -coverage all to xmelab
 
@@ -278,7 +278,7 @@ run_mti : code compile_mti
 
 # Run simulation in interactive mode
 sim_mti : code compile_mti
-	vsim $(MTI_OPTIONS) -gui $(TB_TOP) &
+	cd $(SIM_DIR); vsim $(MTI_OPTIONS) -gui $(TB_TOP) &
 
 # Create work directory
 lib_mti :