Fix VCS simulation and clean up sim makefile

flows/makefile.simulate

@@ -22,7 +22,7 @@ MTI_VC_OPTIONS    += -f $(TBENCH_VC) $(ADP_OPTIONS)
 MTI_RUN_OPTIONS   = -voptargs=+acc
 
 # VCS options
-VCS_OPTIONS    = +vcs+lic+wait +v2k +lint=all,noTMR,noVCDE -debug
+VCS_OPTIONS    = +vcs+lic+wait +v2k -sverilog -override_timescale=1ns/1ps +lint=all,noTMR,noVCDE -debug
 VCS_SIM_OPTION = +vcs+lic+wait +vcs+flush+log -assert nopostproc
 VCS_VC_OPTIONS = -f $(TBENCH_VC) $(ADP_OPTIONS)
 
@@ -73,28 +73,38 @@ compile_mti: NANOSOC_DEFINES += IMEM_0_RAM_PRELOAD
 compile_vcs: NANOSOC_DEFINES += IMEM_0_RAM_PRELOAD
 compile_xm:  NANOSOC_DEFINES += IMEM_0_RAM_PRELOAD
 
+
+# Generate verilog .vc filelist from flists
+flist_vfiles_nanosoc: gen_defs
+	@if [ ! -d $(SIM_DIR) ] ; then \
+	  mkdir -p $(SIM_DIR); \
+	fi
+	@if [ ! -d $(SIM_DIR)/logs ] ; then \
+	  mkdir -p $(SIM_DIR)/logs; \
+	fi
+	@cd $(SIM_DIR); python $(SOCLABS_SOCTOOLS_FLOW_DIR)/bin/filelist_compile.py -f $(TBENCH_VC) -a -v -o tbench.vc
+
+
 # ------- VCS -----------
 
 # Compile RTL
-compile_vcs : gen_defs
-	vcs $(VCS_OPTIONS) $(VCS_VC_OPTIONS) $(DEFINES_VC)  | tee compile_vcs.log
+compile_vcs : gen_defs flist_vfiles_nanosoc
+	cd $(SIM_DIR); vcs $(VCS_OPTIONS) -f tbench.vc  $(DEFINES_VC)  | tee compile_vcs.log
+
 
 # Run simulation in batch mode
-run_vcs : code
-	@if [ ! -d logs ] ; then \
-	  mkdir logs; \
-	fi
-	@echo quit > quit.do
-	./simv $(VCS_SIM_OPTION)                         < quit.do | tee logs/run_$(TESTNAME).log ;
+run_vcs : code compile_vcs
+	@echo quit > $(SIM_DIR)/quit.do
+	cd $(SIM_DIR); ./simv $(VCS_SIM_OPTION) -define ADP_FILE=adp.cmd < quit.do | tee logs/run_$(TESTNAME).log ;
 
 # Run simulation in interactive mode
-sim_vcs : code
-	./simv -gui +vcs+lic+wait +vcs+flush+log &
+sim_vcs : code compile_vcs
+	cd $(SIM_DIR); ./simv -gui +vcs+lic+wait +vcs+flush+log &
 
 # ------- XM -----------
 
 # Compile RTL
-compile_xm : bootrom gen_defs
+compile_xm : bootrom gen_defs flist_vfiles_nanosoc
 	@echo ADP_FILE
 	@echo $(ADP_OPTIONS)
 	cd $(SIM_DIR); xmprep  +overwrite $(XM_VC_OPTIONS) $(DEFINES_VC) +debug -timescale 1ns/1ps -top $(TB_TOP) | tee compile_xm.log
@@ -105,9 +115,6 @@ compile_xm : bootrom gen_defs
 
 # Run simulation in batch mode
 run_xm : code compile_xm
-	@if [ ! -d $(SIM_DIR)/logs ] ; then \
-	  mkdir $(SIM_DIR)/logs; \
-	fi
 	@echo run  >  $(SIM_DIR)/run.tcl.tmp
 	@echo exit >> $(SIM_DIR)/run.tcl.tmp
 	@mv  $(SIM_DIR)/run.tcl.tmp $(SIM_DIR)/run.tcl
@@ -120,21 +127,11 @@ sim_xm : code compile_xm
 # ------- MTI -----------
 
 # Compile RTL
-compile_mti : bootrom gen_defs
-	@mkdir -p $(SIM_DIR)
-	@cd $(SIM_DIR)
-	@if [ -d work ] ; then \
-          true ; \
-	else \
-	  vlib work; \
-	fi
-	cd $(SIM_DIR); vlog -incr -lint +v2k $(MTI_VC_OPTIONS) $(DEFINES_VC) | tee compile_mti.log
+compile_mti : bootrom gen_defs flist_vfiles_nanosoc lib_mti
+	cd $(SIM_DIR); vlog -incr -lint +v2k -f tbench.vc $(ADP_OPTIONS) $(DEFINES_VC) | tee compile_mti.log
 
 # Run simulation in batch mode
 run_mti : code compile_mti
-	@if [ ! -d $(SIM_DIR)/logs ] ; then \
-	  mkdir $(SIM_DIR)/logs; \
-	fi
 	@echo "run -all" > $(SIM_DIR)/run.tcl.tmp
 	@echo "quit -f" >> $(SIM_DIR)/run.tcl.tmp
 	@mv  $(SIM_DIR)/run.tcl.tmp $(SIM_DIR)/run.tcl
@@ -152,7 +149,11 @@ sim_mti : code compile_mti
 
 # Create work directory
 lib_mti :
-	vlib work
+	@if [ -d $(SIM_DIR)/work ] ; then \
+          true ; \
+	else \
+	  vlib  $(SIM_DIR)/work; \
+	fi
 
 # Generate Make filelist from flists
 flist_makefile_nanosoc: gen_defs