Fix RF size and ASIC flow directory

flows/makefile.asic

@@ -56,13 +56,13 @@ PINMAP_FILE           ?= $(TARGET_DIR)/fpga_pinmap.xdc
 RTL_SOCKET_DIR        := $(SOCLABS_SOCDEBUG_TECH_DIR)/socket/vivado_packages
 
 flist_asic_nanosoc: gen_defs
-	@mkdir -p $(TCL_FLIST_DIR)
-	@(cd $(TCL_FLIST_DIR); \
+	@mkdir -p $(TCL_ASIC_FLIST_DIR)
+	@(cd $(TCL_ASIC_FLIST_DIR); \
     $(SOCLABS_SOCTOOLS_FLOW_DIR)/bin/filelist_compile.py -t -s -a -f $(DESIGN_VC) -o $(SYNTHESIS_OUTPUT_FILELIST) -r $(IMP_NANOSOC_ASIC_DIR)/src;)
 
 flist_genus_nanosoc: gen_defs
-	@mkdir -p $(TCL_FLIST_DIR)
-	@(cd $(TCL_FLIST_DIR); \
+	@mkdir -p $(TCL_ASIC_FLIST_DIR)
+	@(cd $(TCL_ASIC_FLIST_DIR); \
 	$(SOCLABS_SOCTOOLS_FLOW_DIR)/bin/filelist_compile.py -t -g -f $(DESIGN_VC) -o $(GENUS_OUTPUT_FILELIST) -r $(IMP_NANOSOC_DIR)/synthesis/src -d $(NANOSOC_DEFINES);)
 
 

synthesis/rf_sp_hdf.spec

@@ -16,7 +16,7 @@ instname = rf_sp_hdf
 left_bus_delim = [
 libertyviewstyle = nldm
 libname = RF_LIB
-mux = 2
+mux = 8
 mvt = 
 name_case = upper
 power_type = otc
@@ -27,7 +27,7 @@ right_bus_delim = ]
 ser = none
 site_def = off
 top_layer = m5-m10
-words = 256
+words = 4096
 wp_size = 1
 write_mask = on
 write_thru = off