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Commit 0c65e808 authored by dwf1m12's avatar dwf1m12
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add extio data channels to QuickStart testbench

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verif/tb/verilog/nanosoc_tb_qs.v
+ 127
− 80
View file @ 0c65e808
//-----------------------------------------------------------------------------
// NanoSoC Testbench adpated from example Cortex-M0 controller testbench - QUICKSTART
// NanoSoC Testbench adpated from example Cortex-M0 controller testbench
// A joint work commissioned on behalf of SoC Labs, under Arm Academic Access license.
//
// Contributors
......@@ -36,12 +36,16 @@
//-----------------------------------------------------------------------------
//
`timescale 1ns/1ps
`include "gen_defines.v"
module nanosoc_tb_qs;
wire CLK; // crystal pin 1
wire TEST; // 0 for system usage
wire NRST; // active low reset
wire NRST_early; // active low reset
wire NRST_late; // active low reset
wire NRST_ext; // active low reset
wire [15:0] P0; // Port 0
wire [15:0] P1; // Port 1
......@@ -64,15 +68,16 @@ module nanosoc_tb_qs;
wire debug_running; // indicate debug test is running
wire debug_err; // indicate debug test has error
wire debug_test_en1;
wire debug_test_en2;
wire debug_test_en1; // UART2 output trace (CMSDK)
wire debug_test_en2; // FT1248 output trace (nanosoc V1)
wire debug_test_en3; // EXTIO output trace (nanosoc V2)
wire debug_test_en; // To enable the debug tester connection to MCU GPIO P0
// This signal is controlled by software,
// Use "UartPutc((char) 0x1B)" to send ESCAPE code to start
// the command, use "UartPutc((char) 0x11)" to send debug test
// enable command, use "UartPutc((char) 0x12)" to send debug test
// disable command. Refer to tb_uart_capture.v file for detail
assign debug_test_en = debug_test_en1 | debug_test_en2; // FT1248 or UART2 control
assign debug_test_en = debug_test_en1 | debug_test_en2 | debug_test_en3; // UART2, FT1248 or EXTIO
//-----------------------------------------
// System options
......@@ -87,7 +92,10 @@ localparam BE=0;
localparam ADP_FILENAME="adp.cmd";
`endif
localparam DATA_IN_FILENAME="data_in.csv";
localparam DATA_OUT_FILENAME="logs/data_out.csv";
/*
SROM_Ax32
#(.ADDRWIDTH (8),
.filename ("bootrom/hex/bootloader.hex"),
......@@ -99,11 +107,30 @@ SROM_Ax32
.SEL(1'b0),
.RDATA( )
);
*/
`ifdef SDF_SIM
initial
$sdf_annotate ( "../../../src/rtl/nanosoc_chip_pads_44pin.sdf"
, u_nanosoc_chip_pads
,
, "sdf_annotate.log"
, "MAXIMUM"
);
`endif // SDF_SIM
`ifdef VCD_SIM
initial begin
$dumpfile("waves.vcd");
$dumpvars(6,u_nanosoc_chip_pads);
end
`endif // VCD_SIM
// --------------------------------------------------------------------------------
// Cortex-M0/Cortex-M0+ Microcontroller
// --------------------------------------------------------------------------------
`ifdef SDF_SIM
nanosoc_chip_pads
u_nanosoc_chip_pads (
`ifdef POWER_PINS
......@@ -115,14 +142,33 @@ SROM_Ax32
`endif
.SE (1'b0),
.CLK (CLK), // input
.TEST (TEST), // output
.TEST (TEST), // input
.NRST (NRST), // active low reset
.P0 (P0),
.P1 (P1),
.P0 (P0[7:0]),
.P1 (P1[7:0]),
.SWDIO (SWDIOTMS),
.SWDCK (SWCLKTCK)
);
`else
nanosoc_chip_pads
u_nanosoc_chip_pads (
`ifdef POWER_PINS
.VDDIO (VDDIO),
.VSSIO (VSSIO),
.VDD (VDD),
.VSS (VSS),
.VDDACC (VDDACC),
`endif
.SE (1'b0),
.CLK (CLK), // input
.TEST (TEST), // input
.NRST (NRST), // active low reset
.P0 (P0[15:0]),
.P1 (P1[15:0]),
.SWDIO (SWDIOTMS),
.SWDCK (SWCLKTCK)
);
`endif
// --------------------------------------------------------------------------------
// Source for clock and reset
// --------------------------------------------------------------------------------
......@@ -130,9 +176,9 @@ SROM_Ax32
nanosoc_clkreset u_nanosoc_clkreset(
.CLK (CLK),
.NRST (NRST),
.NRST_early( ),
.NRST_late ( ),
.NRST_ext ( )
.NRST_early(NRST_early),
.NRST_late (NRST_late),
.NRST_ext (NRST_ext )
);
`endif
......@@ -292,20 +338,6 @@ extio8x4_axis_target u_extio8x4_axis_target
);
`endif
/*
nanosoc_axi_stream_io_8_txd_from_file #(
.TXDFILENAME(ADP_FILENAME),
// .CODEFILENAME("null.hex"),
.FAST_LOAD(FAST_LOAD)
) u_nanosoc_axi_stream_io_dat_txd_from_file (
.aclk (CLK),
.aresetn (NRST),
.txd8_ready (axis_rx1_tready),
.txd8_valid (axis_rx1_tvalid),
.txd8_data (axis_rx1_tdata8)
);
*/
nanosoc_axi_stream_io_8_rxd_to_file#(
.RXDFILENAME("logs/extadp_out.log"),
.VERBOSE(0)
......@@ -325,26 +357,34 @@ extio8x4_axis_target u_extio8x4_axis_target
.RXD8_READY ( ),
.RXD8_VALID (axis_tx0_tvalid & axis_tx0_tready),
.RXD8_DATA (axis_tx0_tdata8),
.DEBUG_TESTER_ENABLE ( ),
.DEBUG_TESTER_ENABLE (debug_test_en3),
.SIMULATIONEND (), // This signal set to 1 at the end of simulation.
.AUXCTRL ()
);
nanosoc_axi_stream_io_8_txd_from_datafile #(
.TXDFILENAME(DATA_IN_FILENAME)
) u_nanosoc_axi_stream_io_8_txd_from_datafile (
.aclk (CLK),
.aresetn (NRST),
.txd8_ready (axis_rx1_tready),
.txd8_valid (axis_rx1_tvalid),
.txd8_data (axis_rx1_tdata8)
);
nanosoc_axi_stream_io_8_rxd_to_file#(
.RXDFILENAME("logs/extdat_out.log")
.RXDFILENAME(DATA_OUT_FILENAME)
) u_nanosoc_axi_stream_io_extdata_8_rxd_to_file (
.aclk (CLK),
.aresetn (NRST),
.eof_received ( ),
.rxd8_ready ( ), //axis_tx1_tready),
.rxd8_valid (axis_tx1_tvalid & axis_tx1_tready),
.rxd8_ready (axis_tx1_tready),
.rxd8_valid (axis_tx1_tvalid),
.rxd8_data (axis_tx1_tdata8)
);
assign axis_tx1_tready = axis_rx1_tready;
assign axis_rx1_tvalid = axis_tx1_tvalid;
assign axis_rx1_tdata8 = axis_tx1_tdata8;
`endif
// --------------------------------------------------------------------------------
......@@ -359,18 +399,6 @@ assign axis_rx1_tdata8 = axis_tx1_tdata8;
// --------------------------------------------------------------------------------
// external UART phase lock to (known) baud rate
// --------------------------------------------------------------------------------
// UART output capture
// --------------------------------------------------------------------------------
`ifdef ARM_CMSDK_SLOWSPEED_PCLK
// If PCLK is running at slower speed, the UART output will also be slower
assign PCLK = u_cmsdk_mcu.u_cmsdk_mcu.PCLK;
`else
assign PCLK = CLK;
`endif
// --------------------------------------------------------------------------------
// external UART phase lock to (known) baud rate
// seem unable to use the following (due to generate instance naming?)
// wire baudx16_clk = u_cmsdk_mcu.u_cmsdk_mcu.u_cmsdk_mcu_system.u_apb_subsystem.u_apb_uart_2.BAUDTICK;
......@@ -390,7 +418,8 @@ assign axis_rx1_tdata8 = axis_tx1_tdata8;
wire baudx16_clk = bauddiv[8]; //prefer:// !baudclken;
wire UARTXD = P1[5];
/// wire UARTXD = P1[5];
wire UARTXD = P1[5] | FT1248MODE; // high if in EXTIO mode
reg UARTXD_del;
always @(negedge NRST or posedge baudx16_clk)
if (!NRST)
......@@ -419,7 +448,6 @@ reg baud_clk_del;
else
baud_clk_del <= baud_clk;
// --------------------------------------------------------------------------------
// set FASTMODE true if UART simulation mode is programmed
wire FASTMODE = 1'b0;
......@@ -431,20 +459,12 @@ reg baud_clk_del;
.RESETn (NRST),
.CLK (uart_clk), //PCLK),
.RXD (UARTXD), // UART 2 use for StdOut
.DEBUG_TESTER_ENABLE (debug_test_en2),
.DEBUG_TESTER_ENABLE (debug_test_en1),
.SIMULATIONEND (), // This signal set to 1 at the end of simulation.
.AUXCTRL ()
);
`endif
// --------------------------------------------------------------------------------
// FTDI IO capture
// --------------------------------------------------------------------------------
// UART connection cross over for UART test
// assign P1[0] = P1[3]; // UART 0 RXD = UART 1 TXD
// assign P1[2] = P1[1]; // UART 1 RXD = UART 0 TXD
// --------------------------------------------------------------------------------
// FTDI IO capture
// --------------------------------------------------------------------------------
......@@ -475,6 +495,7 @@ reg baud_clk_del;
assign ft_miosio_i = (FT1248MODE) ? P1[2] : 1'b0; // & ft_miosio_z;
bufif1 #1 (P1[2], ft_miosio_o, (FT1248MODE & !ft_miosio_z));
//
// AXI stream io testing
//
......@@ -487,10 +508,10 @@ reg baud_clk_del;
wire rxd8_tvalid;
wire [7:0] rxd8_tdata ;
`ifndef COCOTB_SIM
nanosoc_axi_stream_io_8_txd_from_file #(
.TXDFILENAME(ADP_FILENAME),
// .CODEFILENAME("null.hex"),
.FAST_LOAD(FAST_LOAD)
) u_nanosoc_axi_stream_io_8_txd_from_file (
.aclk (CLK),
......@@ -501,7 +522,6 @@ reg baud_clk_del;
);
`endif
nanosoc_ft1248x1_to_axi_streamio_v1_0 u_nanosoc_ft1248x1_to_axi_streamio_v1_0
(
.ft_clk_i (ft_clk_out),
......@@ -541,7 +561,7 @@ nanosoc_track_tb_iostream
.rxd8_ready (rxd8_tready),
.rxd8_valid (rxd8_tvalid),
.rxd8_data (rxd8_tdata),
.DEBUG_TESTER_ENABLE (debug_test_en1),
.DEBUG_TESTER_ENABLE (debug_test_en2),
.AUXCTRL ( ),
.SIMULATIONEND( )
);
......@@ -570,7 +590,7 @@ nanosoc_ft1248x1_track
.RESETn (NRST),
.CLK (ft_clk2uart),
.RXD (ft_rxd2uart),
.DEBUG_TESTER_ENABLE (debug_test_en1),
.DEBUG_TESTER_ENABLE ( ), //debug_test_en2), //driven by u_nanosoc_track_tb_iostream
.SIMULATIONEND (), // This signal set to 1 at the end of simulation.
.AUXCTRL ()
);
......@@ -785,22 +805,21 @@ nanosoc_ft1248x1_track
pulldown(debug_err);
//Tristate logic for GPIO connection
bufif1 (debug_command[5], P0[29-16], debug_test_en);
bufif1 (debug_command[4], P0[28-16], debug_test_en);
bufif1 (debug_command[3], P0[27-16], debug_test_en);
bufif1 (debug_command[2], P0[26-16], debug_test_en);
bufif1 (debug_command[1], P0[25-16], debug_test_en);
bufif1 (debug_command[0], P0[24-16], debug_test_en);
bufif1 (P0[31-16], debug_running, debug_test_en);
bufif1 (P0[30-16], debug_err, debug_test_en);
bufif1 (P0[7], debug_running, debug_test_en);
bufif1 (P0[6], debug_err, debug_test_en);
bufif1 (debug_command[5], P0[5], debug_test_en);
bufif1 (debug_command[4], P0[4], debug_test_en);
bufif1 (debug_command[3], P0[3], debug_test_en);
bufif1 (debug_command[2], P0[2], debug_test_en);
bufif1 (debug_command[1], P0[1], debug_test_en);
bufif1 (debug_command[0], P0[0], debug_test_en);
cmsdk_debug_tester #(.ROM_MEMFILE((BE==1) ? "debugtester_be.hex" : "debugtester_le.hex"))
u_cmsdk_debug_tester
(
// Clock and Reset
.CLK (CLK),
.PORESETn (NRST),
.PORESETn (NRST_ext),
// Command Interface
.DBGCMD (debug_command[5:0]),
......@@ -828,6 +847,34 @@ nanosoc_ft1248x1_track
// Format for time reporting
initial $timeformat(-9, 0, " ns", 0);
// Preload EXP rams
localparam aw_expram_l = u_nanosoc_chip_pads.u_nanosoc_chip.u_system.EXPRAM_L_RAM_ADDR_W;
localparam aw_expram_h = u_nanosoc_chip_pads.u_nanosoc_chip.u_system.EXPRAM_H_RAM_ADDR_W;
localparam awt_expram_l = ((1<<(aw_expram_l-2))-1);
localparam awt_expram_h = ((1<<(aw_expram_h-2))-1);
reg [7:0] fileimage_l [((1<<aw_expram_l)-1):0];
reg [7:0] fileimage_h [((1<<aw_expram_h)-1):0];
integer i,j;
initial begin
$readmemh("expram_l.hex", fileimage_l);
for (i=0;i<awt_expram_l;i=i+1) begin
u_nanosoc_chip_pads.u_nanosoc_chip.u_system.u_ss_expansion.u_region_expram_l.u_expram_l.u_sram.BRAM0[i] = fileimage_l[ 4*i];
u_nanosoc_chip_pads.u_nanosoc_chip.u_system.u_ss_expansion.u_region_expram_l.u_expram_l.u_sram.BRAM1[i] = fileimage_l[(4*i)+1];
u_nanosoc_chip_pads.u_nanosoc_chip.u_system.u_ss_expansion.u_region_expram_l.u_expram_l.u_sram.BRAM2[i] = fileimage_l[(4*i)+2];
u_nanosoc_chip_pads.u_nanosoc_chip.u_system.u_ss_expansion.u_region_expram_l.u_expram_l.u_sram.BRAM3[i] = fileimage_l[(4*i)+3];
end
$readmemh("expram_h.hex", fileimage_h);
for (i=0;i<awt_expram_h;i=i+1) begin
u_nanosoc_chip_pads.u_nanosoc_chip.u_system.u_ss_expansion.u_region_expram_h.u_expram_h.u_sram.BRAM0[i] = fileimage_h[ 4*i];
u_nanosoc_chip_pads.u_nanosoc_chip.u_system.u_ss_expansion.u_region_expram_h.u_expram_h.u_sram.BRAM1[i] = fileimage_h[(4*i)+1];
u_nanosoc_chip_pads.u_nanosoc_chip.u_system.u_ss_expansion.u_region_expram_h.u_expram_h.u_sram.BRAM2[i] = fileimage_h[(4*i)+2];
u_nanosoc_chip_pads.u_nanosoc_chip.u_system.u_ss_expansion.u_region_expram_h.u_expram_h.u_sram.BRAM3[i] = fileimage_h[(4*i)+3];
end
end
// Configuration checks
initial begin
`ifdef CORTEX_M0DESIGNSTART
......
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