makefile

#-----------------------------------------------------------------------------
# NanoSoC Top-Level Makefile 
# - Includes other Makefiles in flow directory
# A joint work commissioned on behalf of SoC Labs, under Arm Academic Access license.
#
# Contributors
#
# David Flynn (d.w.flynn@soton.ac.uk)
#
# Copyright (C) 2021-3, SoC Labs (www.soclabs.org)
#-----------------------------------------------------------------------------

#-------------------------------------
# - Commonly Overloaded Variables
#-------------------------------------
# Name of test directory - Default Test is Hello World
TESTNAME   ?= hello

# Simulator type (mti/vcs/xm)
SIMULATOR   = mti

# Is an accelerator subsystem present in the design?
ACCELERATOR ?= yes

# Is the Arm QuickStart being used?
QUICKSTART ?= no

#-------------------------------------
# - Directory Setups
#-------------------------------------
# Directory of Testcodes
TESTCODES_DIR    := $(SOCLABS_NANOSOC_TECH_DIR)/testcodes

# Project System Directory
FPGA_IMP_DIR     := $(SOCLABS_PROJECT_DIR)/imp/fpga
PROJ_SYS_DIR     := $(SOCLABS_PROJECT_DIR)/system
PROJ_SW_DIR      ?= $(PROJ_SYS_DIR)/testcodes

# Directory to put simulation files
SIM_TOP_DIR ?= $(SOCLABS_PROJECT_DIR)/simulate/sim
SIM_DIR      = $(SIM_TOP_DIR)/$(TESTNAME)

#-------------------------------------
# - Test List Variables
#-------------------------------------
# List of all tests (this is used when running 'make all/clean')
TEST_LIST_FILE   ?= $(TESTCODES_DIR)/software_list.txt
TEST_LIST_FILE   += $(PROJ_SW_DIR)/software_list.txt
TEST_LIST         = $(shell cat $(TEST_LIST_FILE) | while read line || [ -n "$$line" ]; do echo $$line; done)

# List of Tests to Exclude from Regression
EXCLUDE_LIST_FLIE = $(PROJ_SW_DIR)/regression_exclude.txt

#-------------------------------------
# - Verilog Defines and Filelists
#-------------------------------------
# Simulator/Lint Defines
DEFINES_VC  += +define+CORTEX_M0 +define+USE_TARMAC 

# Set Variables depending on whether Accelerator is in System
ifeq ($(ACCELERATOR),yes)
	DEFINES_VC += +define+ACCELERATOR_SUBSYSTEM
	NANOSOC_DEFINES += ACCELERATOR_SUBSYSTEM
endif

# System Design Filelist
ifeq ($(QUICKSTART),yes)
	DESIGN_VC            ?= $(SOCLABS_PROJECT_DIR)/flist/project/top_qs.flist
	TBENCH_VC            ?= $(SOCLABS_PROJECT_DIR)/flist/project/top_qs.flist
	ARM_CORSTONE_101_DIR ?= $(ARM_IP_LIBRARY_PATH)/latest/Cortex-M0-QS/Corstone-101-logical
	ARM_CORTEX_M0_DIR    ?= $(ARM_IP_LIBRARY_PATH)/latest/Cortex-M0-QS/Cortex-M0-logical
	TB_TOP               ?= nanosoc_tb_qs
else
	DESIGN_VC            ?= $(SOCLABS_PROJECT_DIR)/flist/project/top.flist
	TBENCH_VC            ?= $(SOCLABS_PROJECT_DIR)/flist/project/top.flist
	ARM_CORSTONE_101_DIR ?= $(ARM_IP_LIBRARY_PATH)/latest/Corstone-101/logical
	ARM_CORTEX_M0_DIR    ?= $(ARM_IP_LIBRARY_PATH)/latest/Cortex-M0/logical
	TB_TOP               ?= nanosoc_tb
	NANOSOC_DEFINES      += DMAC_0_PL230
endif

# Make variables visible to target shells
export ARM_CORTEX_M0_DIR
export ARM_CORSTONE_101_DIR

# Location of Defines File
DEFINES_DIR   := $(SOCLABS_PROJECT_DIR)/system/src/defines/
DEFINES_FILE  := $(DEFINES_DIR)/gen_defines.v

#------------------------------------------
# - Include Makefiles for Specific Flows
#------------------------------------------
# Include Software Compilation Makefile
include $(SOCLABS_NANOSOC_TECH_DIR)/flows/makefile.software

# Include Linting Makefile
include $(SOCLABS_NANOSOC_TECH_DIR)/flows/makefile.lint

# Include Simulation Makefile
include $(SOCLABS_NANOSOC_TECH_DIR)/flows/makefile.simulate

# Include Regression Simulation Makefile
include $(SOCLABS_NANOSOC_TECH_DIR)/flows/makefile.regression

# Include FPGA Makefile
include $(SOCLABS_NANOSOC_TECH_DIR)/flows/makefile.fpga

#------------------------------------------
# - Common Targets Across Flows
#------------------------------------------
# Generate Defines File for NanoSoC
gen_defs:
	@mkdir -p $(DEFINES_DIR)
	@$(SOCLABS_SOCTOOLS_FLOW_DIR)/bin/defines_compile.py -d $(NANOSOC_DEFINES) -o $(DEFINES_FILE)
	
# Remove RTL compile files, log files, software compile files
clean : clean_all_code
	@rm -rf $(SIM_TOP_DIR)