config_id.h

//-----------------------------------------------------------------------------
// The confidential and proprietary information contained in this file may
// only be used by a person authorised under and to the extent permitted
// by a subsisting licensing agreement from Arm Limited or its affiliates.
//
//            (C) COPYRIGHT 2013 Arm Limited or its affiliates.
//                ALL RIGHTS RESERVED
//
// This entire notice must be reproduced on all copies of this file
// and copies of this file may only be made by a person if such person is
// permitted to do so under the terms of a subsisting license agreement
// from Arm Limited or its affiliates.
//
//      SVN Information
//
//      Checked In          : $Date: 2017-10-10 15:55:38 +0100 (Tue, 10 Oct 2017) $
//
//      Revision            : $Revision: 371321 $
//
//      Release Information : Cortex-M System Design Kit-r1p1-00rel0
//-----------------------------------------------------------------------------
//

#define TEST_PASS 0
#define TEST_FAIL 1
//==============================================================================
// Cortex-M0+ & Cortex-M0 IDs header File
//==============================================================================

// Values used by generic tests, such as debug_tests, romtable_tests

#ifdef CORTEX_M0PLUS
#define MCU_CPU_NAME "Cortex-M0+"
#define MCU_CPU_ID_VALUE  0x410cc601
#define MCU_DP_IDR_VALUE  0x0BC11477
#define MCU_AP_IDR_VALUE  0x04770031
#define MCU_AP_BASE_VALUE 0xF0000003
#else
#define MCU_CPU_NAME "Cortex-M0"
#define MCU_CPU_ID_VALUE  0x410cc200
#define MCU_DP_IDR_VALUE  0x0BB11477
#define MCU_AP_IDR_VALUE  0x04770021
#define MCU_AP_BASE_VALUE 0xE00FF003
#endif

//==============================================================================
//
// GenericID values - DO NOT MODIFY
//

// CoreSight Component Identifier for Peripheral classes
#define CORESIGHT_CID0          0x0D
#define CORESIGHT_CID1_tbl      0x10
#define CORESIGHT_CID1_dbg      0x90
#define CORESIGHT_CID1_mem      0xE0
#define CORESIGHT_CID1_prm      0xF0
#define CORESIGHT_CID2          0x05
#define CORESIGHT_CID3          0xB1

// Component Part Numbers
#define ARM_JEP_ID              0x3B
#define ARM_JEP_CONT            0x4

//==============================================================================
//
// Cortex-M0 ID values
#define CORTEXM0_CPUID          0x410cc200

#define CM0_CPU_PART            0x471
#define CM0_SCS_PART            0x008