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nanosoc_cpu.v
SOC1-167: WIP: Restructured verilog file to seperate rtl into groups
dam1n19 authored
nanosoc_cpu.v 9.32 KiB
//-----------------------------------------------------------------------------
// customised Cortex-M0 'nanosoc' controller
// A joint work commissioned on behalf of SoC Labs, under Arm Academic Access license.
//
// Contributors
//
// David Flynn (d.w.flynn@soton.ac.uk)
//
// Copyright 2021-3, SoC Labs (www.soclabs.org)
//-----------------------------------------------------------------------------
//-----------------------------------------------------------------------------
// The confidential and proprietary information contained in this file may
// only be used by a person authorised under and to the extent permitted
// by a subsisting licensing agreement from Arm Limited or its affiliates.
//
// (C) COPYRIGHT 2010-2013 Arm Limited or its affiliates.
// ALL RIGHTS RESERVED
//
// This entire notice must be reproduced on all copies of this file
// and copies of this file may only be made by a person if such person is
// permitted to do so under the terms of a subsisting license agreement
// from Arm Limited or its affiliates.
//
// SVN Information
//
// Checked In : $Date: 2017-10-10 15:55:38 +0100 (Tue, 10 Oct 2017) $
//
// Revision : $Revision: 371321 $
//
// Release Information : Cortex-M System Design Kit-r1p1-00rel0
//
//-----------------------------------------------------------------------------
//-----------------------------------------------------------------------------
// Abstract : System level design for the example Cortex-M0 system
//-----------------------------------------------------------------------------
module nanosoc_cpu #(
parameter CLKGATE_PRESENT = 0,
parameter BE = 0, // 1: Big endian 0: little endian
parameter BKPT = 4, // Number of breakpoint comparators
parameter DBG = 1, // Debug configuration
parameter NUMIRQ = 32, // NUM of IRQ
parameter SMUL = 0, // Multiplier configuration
parameter SYST = 1, // SysTick
parameter WIC = 1, // Wake-up interrupt controller support
parameter WICLINES = 34, // Supported WIC lines
parameter WPT = 2, // Number of DWT comparators
parameter RESET_ALL_REGS = 0, // Do not reset all registers
parameter INCLUDE_JTAG = 0 // Do not Include JTAG feature
)
(
input wire HCLK, // (HCLK master)
input wire FCLK, // Free running clock
input wire SCLK, // System clock
input wire HRESETn, // AHB and System reset
input wire PORESETn, // Power on reset
input wire DCLK, // Debug clock
input wire DBGRESETn, // Debug reset
input wire RSTBYPASS, // Reset by pass (for testing)
input wire DFTSE, // Reset by pass (for testing)
// AHB Lite port
output wire [31:0] HADDR, // Address bus
output wire [1:0] HTRANS, // Transfer type
output wire HWRITE, // Transfer direction
output wire [2:0] HSIZE, // Transfer size
output wire [2:0] HBURST, // Burst type
output wire [3:0] HPROT, // Protection control
output wire [31:0] HWDATA, // Write data output wire HMASTLOCK, // Locked Sequence
// output wire [1:0] HAUSER, // Address USER signals
// output wire [1:0] HWUSER, // Write-data USER signals
input wire [31:0] HRDATA, // Read data bus
input wire HREADY, // HREADY feedback
input wire HRESP, // Transfer response
// input wire [1:0] HRUSER, // Read-data USER signals
// Sideband CPU signalling
input wire NMI, // Non-Maskable Interrupt request
input wire [31:0] IRQ, // Maskable Interrupt requests
output wire TXEV, // Send Event (SEV) output
input wire RXEV, // Receive Event input
output wire SLEEPING, // Processor status - sleeping
output wire SLEEPDEEP, // Processor status - deep sleep
output wire GATEHCLK, // Wake up request from WIC
output wire LOCKUP, // Wake up request from WIC
output wire WAKEUP, // Wake up request from WIC
input wire WICENREQ, // WIC enable request from PMU
output wire WICENACK, // WIC enable ack to PMU
input wire SLEEPHOLDREQn, // Sleep extension request from PM
output wire SLEEPHOLDACKn, // Sleep extension request to PMU
input wire CDBGPWRUPREQ, // Sleep extension request from PM
output wire CDBGPWRUPACK, // Sleep extension request to PMU
input wire SYSRESETREQ, // System reset request
input wire WDOGRESETREQ, // Watchdog reset request
input wire ADPRESETREQ, // ADP Debug reset request
// Serial-Wire Debug
input wire SWDI, // SWD data input
input wire SWCLK, // SWD clock
output wire SWDO, // SWD data output
output wire SWDOEN); // SWD data output enable
// -------------------------------
// Internal signals
// -------------------------------
// clock, reset, and power control
wire [33:0] WICSENSE;
wire APBACTIVE; // APB bus active (for clock gating of PCLKG)
wire LOCKUPRESET; // System Controller cfg - reset if lockup
wire PMUENABLE; // System Controller cfg - Enable PMU
// SysTick timer signals
wire STCLKEN;
wire [25:0] STCALIB;
// Processor debug signals
wire DBGRESTART;
wire DBGRESTARTED;
wire EDBGRQ;
// Processor status
wire HALTED;
wire [2:0] CODEHINTDE;
wire SPECHTRANS;
wire CODENSEQ;
wire SHAREABLE;
// Cortex-M0 integration level
CORTEXM0INTEGRATION
#(.ACG (CLKGATE_PRESENT), // Architectural clock gating
.BE (BE), // Big-endian
.BKPT (BKPT), // Number of breakpoint comparators
.DBG (DBG), // Debug configuration
.JTAGnSW (INCLUDE_JTAG), // Debug port interface: JTAGnSW .NUMIRQ (NUMIRQ), // Number of Interrupts
.RAR (RESET_ALL_REGS), // Reset All Registers
.SMUL (SMUL), // Multiplier configuration
.SYST (SYST), // SysTick
.WIC (WIC), // Wake-up interrupt controller support
.WICLINES (WICLINES), // Supported WIC lines
.WPT (WPT)) // Number of DWT comparators
u_cortex_m0_integration (
// System inputs
.FCLK (FCLK), // FCLK
.SCLK (SCLK), // SCLK generated from PMU
.HCLK (HCLK), // HCLK generated from PMU
.DCLK (DCLK), // DCLK generated from PMU
.PORESETn (PORESETn),
.HRESETn (HRESETn),
.DBGRESETn (DBGRESETn),
.RSTBYPASS (RSTBYPASS),
.SE (DFTSE),
// Power management inputs
.SLEEPHOLDREQn (SLEEPHOLDREQn),
.WICENREQ (WICENREQ),
.CDBGPWRUPACK (CDBGPWRUPACK),
// Power management outputs
.SLEEPHOLDACKn (SLEEPHOLDACKn),
.WICENACK (WICENACK),
.CDBGPWRUPREQ (CDBGPWRUPREQ),
.WAKEUP (WAKEUP),
.WICSENSE (WICSENSE),
.GATEHCLK (GATEHCLK),
.SYSRESETREQ (SYSRESETREQ),
// System bus
.HADDR (HADDR ),
.HTRANS (HTRANS ),
.HSIZE (HSIZE ),
.HBURST (HBURST ),
.HPROT (HPROT ),
.HMASTLOCK (HMASTLOCK ),
.HWRITE (HWRITE ),
.HWDATA (HWDATA ),
.HRDATA (HRDATA ),
.HREADY (HREADY ),
.HRESP (HRESP ),
.HMASTER ( ),
.CODEHINTDE (CODEHINTDE),
.SPECHTRANS (SPECHTRANS),
.CODENSEQ (CODENSEQ),
// Interrupts
.IRQ (IRQ[31:0]),
.NMI (NMI),
.IRQLATENCY (8'h00),
.ECOREVNUM (28'h0),
// Systick
.STCLKEN (STCLKEN),
.STCALIB (STCALIB),
// Debug - JTAG or Serial wire
// inputs
.nTRST (1'b1),
.SWDITMS (SWDI),
.SWCLKTCK (SWCLK),
.TDI (1'b0),
// outputs .TDO ( ),
.nTDOEN ( ),
.SWDO (SWDO),
.SWDOEN (SWDOEN),
.DBGRESTART (DBGRESTART),
.DBGRESTARTED (DBGRESTARTED),
// Event communication
.TXEV (TXEV),
.RXEV (RXEV),
.EDBGRQ (EDBGRQ),
// Status output
.HALTED (HALTED),
.LOCKUP (LOCKUP),
.SLEEPING (SLEEPING),
.SLEEPDEEP (SLEEPDEEP)
);
// Unused debug feature
assign DBGRESTART = 1'b0; // multi-core synchronous restart from halt
assign EDBGRQ = 1'b0; // multi-core synchronous halt request
// -------------------------------
// SysTick signals
// -------------------------------
cmsdk_mcu_stclkctrl
#(.DIV_RATIO (18'd01000))
u_cmsdk_mcu_stclkctrl (
.FCLK (FCLK),
.SYSRESETn (HRESETn),
.STCLKEN (STCLKEN),
.STCALIB (STCALIB)
);
endmodule