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SoCLabs
FPGA Library Tech
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3e6eea8f70104378841ddb7032399cebcf43686f to 4344fb7198daaae6d40f95b58587af5f869263a2
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Modified sram wrapper
· 4344fb71
dam1n19
authored
1 year ago
4344fb71
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sram/verilog/sl_ahb_sram.v
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sram/verilog/sl_ahb_sram.v
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sram/verilog/sl_ahb_sram.v
View file @
4344fb71
...
...
@@ -12,7 +12,6 @@
module
sl_ahb_sram
#(
// System Parameters
parameter
SYS_ADDR_W
=
32
,
// System Address Width
parameter
SYS_DATA_W
=
32
,
// System Data Width
parameter
RAM_ADDR_W
=
14
,
// Size of SRAM
parameter
RAM_DATA_W
=
32
,
// Data Width of RAM
...
...
@@ -29,7 +28,7 @@ module sl_ahb_sram #(
input
wire
[
2
:
0
]
HSIZE
,
// AHB hsize
input
wire
HWRITE
,
// AHB hwrite
input
wire
[
RAM_ADDR_W
-
1
:
0
]
HADDR
,
// AHB address bus
input
wire
[
3
1
:
0
]
HWDATA
,
// AHB write data bus
input
wire
[
SYS_DATA_W
-
1
:
0
]
HWDATA
,
// AHB write data bus
output
wire
HREADYOUT
,
// AHB ready output to S->M mux
output
wire
HRESP
,
// AHB response
output
wire
[
SYS_DATA_W
-
1
:
0
]
HRDATA
// AHB read data bus
...
...
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