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Commit 5e31b45c authored by Daniel Newbrook's avatar Daniel Newbrook
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Initial behavioural version using cocotb

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#-----------------------------------------------------------------------------
# MilliSoC expansion Simulation Makefile
# A joint work commissioned on behalf of SoC Labs, under Arm Academic Access license.
#
# Contributors
#
# David Mapstone (d.a.mapstone@soton.ac.uk)
# Daniel Newbrook (d.newbrook@soton.ac.uk)
# Copyright (C) 2021-4, SoC Labs (www.soclabs.org)
#-----------------------------------------------------------------------------
module SRAM (
input wire clk,
input wire [13:0] memaddr,
input wire [127:0] memd,
output wire [127:0] memq,
input wire memcen,
input wire [15:0] memwen
);
parameter MEM_DEPTH = (1<<10);
wire WriteEnable; // Write data update
wire [10:0] Addr;
reg [127:0] DataAtAddress; // Current write-data at address
reg [127:0] Mask; // Write data-mask
reg [127:0] NextData; // Next write-data
reg [127:0] iQ; // Memory output data (pipelined)
integer i; // Write-strobe loop variable
integer j; // Mask-bit loop variable
assign Addr = memaddr[13:4];
// -------------
// Memory arrays
// -------------
// Memory array 0 - used in both 32-bit and 64-bit modes
reg [127:0] mem [MEM_DEPTH-1:0];
assign WriteEnable = (memwen != {16{1'b1}}) ? 1'b1 : 1'b0;
always @ (posedge clk)
begin : p_memaccess
// Only access the memory when the chip is enabled
if (!memcen)
begin
// Look-up the data at the current address
DataAtAddress[127:0] = mem[Addr];
// Update the memory and the data output only when permitted
if (WriteEnable)
begin
// Determine the byte-lane mask value by testing the individual
// bits of the active-low write strobes
for (i = 0; i < 16; i = i + 1)
for (j = i * 8; j <= (i * 8) + 7; j = j + 1)
Mask[j] = ~memwen[i];
// Determine the value of the next write-data. Term (a) clears
// the required byte lanes and term (b) selects the required
// byte-lanes of the AXI write data. The two data words are
// bit-wise OR'ed together to form the new data word
NextData = (DataAtAddress & ~Mask) | // (a)
(memd & Mask); // (b)
mem[Addr] = NextData[127:0]; // Always assign mem array 0
// Update the data output with new data
iQ <= NextData;
end
else
// Update the data output with the original data value
iQ <= DataAtAddress;
end
end
// Drive read data output port at the selected stage of the pipeline
assign memq = iQ;
endmodule
module SRAM_wrapper(
input wire ACLK,
input wire ARESETn,
input wire AWVALID,
output wire AWREADY,
input wire [3:0] AWID,
input wire [31:0] AWADDR,
input wire [7:0] AWLEN,
input wire [2:0] AWSIZE,
input wire [1:0] AWBURST,
input wire AWLOCK,
input wire [2:0] AWPROT,
input wire [3:0] AWQOS,
input wire WVALID,
output wire WREADY,
input wire [127:0] WDATA,
input wire [15:0] WSTRB,
input wire WLAST,
input wire [1:0] WPOISON,
output wire BVALID,
input wire BREADY,
output wire [3:0] BID,
output wire [1:0] BRESP,
input wire ARVALID,
output wire ARREADY,
input wire [3:0] ARID,
input wire [31:0] ARADDR,
input wire [7:0] ARLEN,
input wire [2:0] ARSIZE,
input wire [1:0] ARBURST,
input wire ARLOCK,
input wire [2:0] ARPROT,
input wire [3:0] ARQOS,
output wire RVALID,
input wire RREADY,
output wire [3:0] RID,
output wire [127:0] RDATA,
output wire [1:0] RRESP,
output wire RLAST,
output wire [1:0] RPOISON,
input wire AWAKEUP,
input wire clk_qreqn,
output wire clk_qacceptn,
output wire clk_qdeny,
output wire clk_qactive,
input wire pwr_qreqn,
output wire pwr_qacceptn,
output wire pwr_qdeny,
output wire pwr_qactive,
input wire ext_gt_qreqn,
output wire ext_gt_qacceptn,
input wire cfg_gate_resp
);
wire [13:0] memaddr;
wire [127:0] memd;
wire [127:0] memq;
wire memcen;
wire [15:0] memwen;
sie300_axi5_sram_ctrl_millisoc_exp u_SMC(
.aclk(ACLK),
.aresetn(ARESETn),
.awvalid_s(AWVALID),
.awready_s(AWREADY),
.awid_s(AWID),
.awaddr_s(AWADDR[13:0]),
.awlen_s(AWLEN),
.awsize_s(AWSIZE),
.awburst_s(AWBURST),
.awlock_s(AWLOCK),
.awprot_s(AWPROT),
.awqos_s(AWQOS),
.wvalid_s(WVALID),
.wready_s(WREADY),
.wdata_s(WDATA),
.wstrb_s(WSTRB),
.wlast_s(WLAST),
.wpoison_s(WPOISON),
.bvalid_s(BVALID),
.bready_s(BREADY),
.bid_s(BID),
.bresp_s(BRESP),
.arvalid_s(ARVALID),
.arready_s(ARREADY),
.arid_s(ARID),
.araddr_s(ARADDR[13:0]),
.arlen_s(ARLEN),
.arsize_s(ARSIZE),
.arburst_s(ARBURST),
.arlock_s(ARLOCK),
.arprot_s(ARPROT),
.arqos_s(ARQOS),
.rvalid_s(RVALID),
.rready_s(RREADY),
.rid_s(RID),
.rdata_s(RDATA),
.rresp_s(RRESP),
.rlast_s(RLAST),
.rpoison_s(RPOISON),
.awakeup_s(AWAKEUP),
.clk_qreqn(clk_qreqn),
.clk_qacceptn(clk_qacceptn),
.clk_qdeny(clk_qdeny),
.clk_qactive(clk_qactive),
.pwr_qreqn(pwr_qreqn),
.pwr_qacceptn(pwr_qacceptn),
.pwr_qdeny(pwr_qdeny),
.pwr_qactive(pwr_qactive),
.ext_gt_qreqn(ext_gt_qreqn),
.ext_gt_qacceptn(ext_gt_qacceptn),
.cfg_gate_resp(cfg_gate_resp),
.memaddr(memaddr),
.memd(memd),
.memq(memq),
.memcen(memcen),
.memwen(memwen)
);
SRAM u_SRAM(
.clk(ACLK),
.memaddr(memaddr),
.memd(memd),
.memq(memq),
.memcen(memcen),
.memwen(memwen)
);
endmodule
\ No newline at end of file
module expansion_region(
input wire clk,
input wire resetn,
input wire [2:0] AWID_AXI_EXPANSION,
input wire [31:0] AWADDR_AXI_EXPANSION,
input wire [7:0] AWLEN_AXI_EXPANSION,
input wire [2:0] AWSIZE_AXI_EXPANSION,
input wire [1:0] AWBURST_AXI_EXPANSION,
input wire AWLOCK_AXI_EXPANSION,
input wire [3:0] AWCACHE_AXI_EXPANSION,
input wire [2:0] AWPROT_AXI_EXPANSION,
input wire AWVALID_AXI_EXPANSION,
output wire AWREADY_AXI_EXPANSION,
input wire [127:0] WDATA_AXI_EXPANSION,
input wire [15:0] WSTRB_AXI_EXPANSION,
input wire WLAST_AXI_EXPANSION,
input wire WVALID_AXI_EXPANSION,
output wire WREADY_AXI_EXPANSION,
output wire [2:0] BID_AXI_EXPANSION,
output wire [1:0] BRESP_AXI_EXPANSION,
output wire BVALID_AXI_EXPANSION,
input wire BREADY_AXI_EXPANSION,
input wire [2:0] ARID_AXI_EXPANSION,
input wire [31:0] ARADDR_AXI_EXPANSION,
input wire [7:0] ARLEN_AXI_EXPANSION,
input wire [2:0] ARSIZE_AXI_EXPANSION,
input wire [1:0] ARBURST_AXI_EXPANSION,
input wire ARLOCK_AXI_EXPANSION,
input wire [3:0] ARCACHE_AXI_EXPANSION,
input wire [2:0] ARPROT_AXI_EXPANSION,
input wire ARVALID_AXI_EXPANSION,
output wire ARREADY_AXI_EXPANSION,
output wire [2:0] RID_AXI_EXPANSION,
output wire [127:0] RDATA_AXI_EXPANSION,
output wire [1:0] RRESP_AXI_EXPANSION,
output wire RLAST_AXI_EXPANSION,
output wire RVALID_AXI_EXPANSION,
input wire RREADY_AXI_EXPANSION
);
endmodule
\ No newline at end of file
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DMA350_IP_LOGICAL_DIR:=
SIE300_IP_LOGICAL_DIR:=
\ No newline at end of file
makefile 0 → 100644
#-----------------------------------------------------------------------------
# milliSoC Expansion region Top-Level Makefile
# - Includes other Makefiles in flow directory
# A joint work commissioned on behalf of SoC Labs, under Arm Academic Access l
#
# Contributors
#
# David Flynn (d.w.flynn@soton.ac.uk)
# Daniel Newbrook (d.newbrook@soton.ac.uk)
# Copyright (C) 2021-3, SoC Labs (www.soclabs.org)
#-----------------------------------------------------------------------------
include ./flows/makefile.simulate
include ./make.cfg
build_dma350:
@$(DMA350_IP_LOGICAL_DIR)/generate --config ./socrates/DMA350/config/cfg_dma_axi.yaml --output ./logical/dma350/
build_sie300_sram_ctrl:
@$(SIE300_IP_LOGICAL_DIR)/generate --config ./socrates/BP301_SRAM/config/SRAM_ctrl.yaml --output ./logical/SMC
build_nic400:
socrates_cli --project millisoc_expansion -data ../ --flow build.configured.component configuredComponentName=nic400_millisoc_expansion
build_ip: build_dma350 build_sie300_sram_ctrl build_nic400
make_project:
socrates_cli --project millisoc_expansion -data ../ --flow AddNewProject
first_time_setup: make_project build_ip
all: first_time_setup
clean:
@rm -rf ./logical/dma350
@rm -rf ./logical/nic400_millisoc_expansion
@rm -rf ./logical/shared/ipxact
@rm -rf ./logical/SMC
export SOCLABS_MILLISOC_EXP_DIR=$(pwd)
\ No newline at end of file
#----------------------------------------------------------------------------
# The confidential and proprietary information contained in this file may
# only be used by a person authorised under and to the extent permitted
# by a subsisting licensing agreement from Arm Limited or its affiliates.
#
# (C) COPYRIGHT 2019 Arm Limited or its affiliates.
# ALL RIGHTS RESERVED
#
# This entire notice must be reproduced on all copies of this file
# and copies of this file may only be made by a person if such person is
# permitted to do so under the terms of a subsisting license agreement
# from Arm Limited or its affiliates.
#----------------------------------------------------------------------------
#
# Version Information
#
# Checked In : Mon Jul 15 17:15:15 2019 +0100
#
# Revision : 828f11fd
#
# Release Information : CoreLink SIE-300 Generic Global Bundle r1p2-00rel0
#
#----------------------------------------------------------------------------
# Abstract : Configuration file for SIE-300 AXI5 SRAM Controller
#----------------------------------------------------------------------------
# -----------------------------
# User Configuration
# -----------------------------
#
# COMPONENT: Name of the component to configure.
# Valid values:
# [sie300_axi5_sram_ctrl]
#
COMPONENT: sie300_axi5_sram_ctrl
#
# CONFIG_NAME: Name of the configuration.
# Each unifiqued element and top is suffixed with
# _${CONFIG_NAME}
#
CONFIG_NAME: millisoc_exp
#
# ADDR_WIDTH: AXI5 Address Bus width
# Valid values:
# 14-24
ADDR_WIDTH: 14
#
# DATA_WIDTH: AXI5 Data Bus width
# Valid values:
# [32,64,128,256]
DATA_WIDTH: 128
#
# ID_WIDTH: AXI5 ID width for all channels
# Valid values:
# 2-32
ID_WIDTH: 4
#
# QCLK_SYNC_EN: Add 2 DFF synchronizer on inputs of clock Q-channel
# Valid values:
# - 0 : no synchronizer
# - 1 : added synchronizer
QCLK_SYNC_EN: 1
#
# QPWR_SYNC_EN: Add 2 DFF synchronizer on inputs of power Q-channel
# Valid values:
# - 0 : no synchronizer
# - 1 : added synchronizer
QPWR_SYNC_EN: 1
#
# QEXT_SYNC_EN: Add 2 DFF synchronizer on inputs of external gating Q-channel
# Valid values:
# - 0 : no synchronizer
# - 1 : added synchronizer
QEXT_SYNC_EN: 1
#
# EXCLUSIVE_MONITORS: Number of Exclusive Access Monitors to observe
# and track AXI locked transactions
# Valid values:
# 0-16 (0 means no locked transaction support)
EXCLUSIVE_MONITORS: 2
#
# AR_BUF_SIZE: Size of FIFO on AR channel
# Valid values:
# 1-16
AR_BUF_SIZE: 1
#
# AW_BUF_SIZE: Size of FIFO on AW channel
# Valid values:
# 1-16
AW_BUF_SIZE: 2
#
# W_BUF_SIZE: Size of FIFO on W channel
# Valid values:
# 1-16
W_BUF_SIZE: 8
#
# REGISTER_AXI_AR: Enables / disables register stage at the AR FIFO
# Valid values:
# [BYPASS,FULL]
REGISTER_AXI_AR: BYPASS
#
# REGISTER_AXI_R: Enables / disables register stage at the R FIFO
# Valid values:
# [BYPASS,FULL]
REGISTER_AXI_R: BYPASS
#
# AXI5_POISON_EN: Enables / disables AXI5 Data Poisoning support
# Valid values:
# [0,1]
AXI5_POISON_EN: 0
#----------------------------------------------------------------------------
# The confidential and proprietary information contained in this file may
# only be used by a person authorised under and to the extent permitted
# by a subsisting licensing agreement from Arm Limited or its affiliates.
#
# (C) COPYRIGHT 2021-2022 Arm Limited or its affiliates.
# ALL RIGHTS RESERVED
#
# This entire notice must be reproduced on all copies of this file
# and copies of this file may only be made by a person if such person is
# permitted to do so under the terms of a subsisting license agreement
# from Arm Limited or its affiliates.
#----------------------------------------------------------------------------
#
# Release Information : DMA350-r0p0-00rel0
#
# -----------------------------------------------------------------------------
# Abstract : User Configuration file for ADA DMA
# -----------------------------------------------------------------------------
#
# CONFIG_NAME: Name of the configuration.
# Each unifiqued element and top is suffixed with
# _${CONFIG_NAME}
#
CONFIG_NAME: sldma350
#
# ADDR_WIDTH: Address Bus width
#
# Valid values:
# 32-64
ADDR_WIDTH: 32
#
# DATA_WIDTH: Data Bus width
#
# Valid values:
# [32,64,128]
DATA_WIDTH: 128
#
# CHID_WIDTH: Width of the configurable channel ID user signal.
# When set to 0, then the archid and awchid ports are not present on the module.
#
# Valid values:
# 0-16
CHID_WIDTH: 0
#
# GPO_WIDTH: Width of GPO output for every channel. When multiple channels have GPOs
# then the width must be set to the maximum number of GPOs a channel can have,
# and unused GPO ports need to be left unconnected. When all bits of CH_GPO_MASK
# is 0, this parameter is not relevant.
#
# Valid values:
# 1-32
GPO_WIDTH: 1
#
# CH_GPO_MASK: A bitmask for enabling the GPO port for each channel. The width of the
# bitmask is NUM_CHANNELS-1. When bit n is set to 1 then the GPO is enabled for
# channel n and the gpo_ch_n[GPO_WIDTH-1:0] port appears on the module.
#
# Valid values:
# 0-(2^NUM_CHANNELS-1)
CH_GPO_MASK: 0x3
#
# CH_STREAM_MASK: A bitmask for enabling the stream interfaces for each channel.
# The width of the bitmask is NUM_CHANNELS-1. When bit n is set to 1 then
# the stream interfaces are enabled for channel n and the relevant ports
# appears on the module. NOTE: When streaming interface is enabled the actual
# FIFO size of the channel will be the double of CH_<N>_FIFO_DEPTH
#
# Valid values:
# 0-(2^NUM_CHANNELS-1)
CH_STREAM_MASK: 0x3
#
# CH_<N>_FIFO_DEPTH: Sets the FIFO depth for channel <N> that defines the number of
# DATA_WIDTH size entries a channel can hold for a transfer. N goes from 0 to
# NUM_CHANNELS-1. In combination with the TRANSIZE setting of the command, the
# FIFO depth defines the maximum burst size a channel can support. This setting
# needs to be aligned with the bandwidth requirements of the channel but it
# highly affects the area of the design.
#
# Valid values:
# [1,2,4,8,16,32,64]
CH_0_FIFO_DEPTH: 32
CH_1_FIFO_DEPTH: 32
CH_2_FIFO_DEPTH: 32
CH_3_FIFO_DEPTH: 32
#
# CH_EXT_FEAT_MASK: A bitmask for enabling the extended feature set for each channel.
# The extension contains 2D, WRAP, TMPLT features. Default value enables it for
# the number of channels.
#
# Valid values:
# 0-(2^NUM_CHANNELS-1)
CH_EXT_FEAT_MASK: 0x3
#
# NUM_CHANNELS: Number of configurable DMA channels.
#
# Valid values:
# 1-8
NUM_CHANNELS: 4
#
# NUM_TRIGGER_IN: Number of trigger input ports.
#
# Valid values:
# 0-32
NUM_TRIGGER_IN: 2
#
# NUM_TRIGGER_OUT: Number of trigger output ports.
#
# Valid values:
# 0-32
NUM_TRIGGER_OUT: 2
#
# TRIG_IN_SYNC_EN_MASK: A bitmask for enabling the synchronizers on the trigger in
# interfaces for each trigger port. The width of the bitmask is NUM_TRIGGER_IN-1.
# When bit n is set to 1 then the trigger in interface is considered asynchronous
# and the synchronizer logic is placed on the selected input ports.
#
# Valid values:
# 0-(2^NUM_TRIGGER_IN-1)
TRIG_IN_SYNC_EN_MASK: 0x0
#
# TRIG_OUT_SYNC_EN_MASK: A bitmask for enabling the synchronizers on the trigger out
# interfaces for each trigger port. The width of the bitmask is NUM_TRIGGER_OUT-1.
# When bit n is set to 1 then the trigger out interface is considered asynchronous
# and the synchronizer logic is placed on the selected input ports.
#
# Valid values:
# 0-(2^NUM_TRIGGER_OUT-1)
TRIG_OUT_SYNC_EN_MASK: 0x0
#
# AXI5_M1_PRESENT: Enables an additional master port. When set the m1 master port is
# present on the top level port list and additional include file can be used with
# a System Verilog function that defines which address ranges are mapped to the m1
# interface.
#
# Valid values:
# [0,1]
AXI5_M1_PRESENT: 1
#
# SECEXT_PRESENT: Enables TrustZone security support.
#
# Valid values:
# [0,1]
SECEXT_PRESENT: 0
#
# AXI5_M1_ADDR_MAP: Select AXI M1 master.
#
# Valid values:
# relative path to logical
AXI5_M1_ADDR_MAP: models/modules/generic/address_map_m1_cocotb.sv
This diff is collapsed.
import itertools
import logging
import os
from numpy import random
import numpy as np
import cocotb
from cocotb.clock import Clock
from cocotb.triggers import RisingEdge, Timer
from cocotb.regression import TestFactory
from cocotbext.axi import AxiBus, AxiMaster, AxiBurstType
DMA350_BASE = 0x600C0000
DMASECCFG_S_BASE = DMA350_BASE + 0x0000
DMASECCTRL_S_BASE = DMA350_BASE + 0x0100
DMANSECCTRL_S_BASE = DMA350_BASE + 0x0200
DMAINFO_S_BASE = DMA350_BASE + 0x0F00
DMACH0_S_BASE = DMA350_BASE + 0x1000
DMACH1_S_BASE = DMA350_BASE + 0x1100
async def AdaGetChNum(dut, tb):
DMA_BUILDCFG0 = await tb.axi_master.read_dword(DMAINFO_S_BASE+0xB0)
await RisingEdge(dut.sys_clk)
await RisingEdge(dut.sys_clk)
num_ch = DMA_BUILDCFG0 & 0x1F8
num_ch = num_ch >> 4
return num_ch + 1
async def AdaGetIIDR(dut,tb):
IIDR = await tb.axi_master.read_dword(DMAINFO_S_BASE+0xC8)
await RisingEdge(dut.sys_clk)
await RisingEdge(dut.sys_clk)
return IIDR
async def AdaSetSourceAddress(dut, tb, ch, src_address):
await tb.axi_master.write_dword(DMACH0_S_BASE+0x010+(ch<<8), src_address, byteorder='little')
async def AdaSetDestAddress(dut, tb, ch, dst_address):
await tb.axi_master.write_dword(DMACH0_S_BASE+0x018+(ch<<8), dst_address, byteorder='little')
async def AdaSetTranSize(dut, tb, ch, SrcSize, DstSize):
await tb.axi_master.write_dword(DMACH0_S_BASE+0x020+(ch<<8), ((DstSize<<16)+SrcSize), byteorder='little')
async def AdaSetChControl(dut, tb, ch, TRANSIZE, CHPRIO, XTYPE, YTYPE, REGRELOADTYPE, DONETYPE, DONEPAUSEEN, USESRCTRIGIN, USEDESTRIGIN, USETRIGOUT, USEGPO, USESTREAM):
data = TRANSIZE.value
data += (CHPRIO & 0xF) << 4
data += (XTYPE.value & 0x7) << 9
data += (YTYPE.value & 0x7) << 12
data += (REGRELOADTYPE & 0x7) << 18
data += (DONETYPE & 0x7) << 21
data += (DONEPAUSEEN & 0x1) << 24
data += (USESRCTRIGIN & 0x1) << 25
data += (USEDESTRIGIN & 0x1) << 26
data += (USETRIGOUT & 0x1) << 27
data += (USEGPO & 0x1) << 28
data += (USESTREAM & 0x1) << 29
await tb.axi_master.write_dword(DMACH0_S_BASE+0x00C + (ch<<8), data, byteorder='little')
async def AdaSetChDESTRANSCFG(dut, tb, ch, DESMEMATTRLO, DESMEMATTRHI, DESSHAREATTR, DESNONSECATTR, DESPRIVATTR, DESMAXBURSTLEN):
data = DESMEMATTRLO & 0x7
data += (DESMEMATTRHI & 0x7) << 4
data += (DESSHAREATTR & 0x3) << 8
data += (DESNONSECATTR & 0x1) << 10
data += (DESPRIVATTR & 0x1) << 11
data += (DESMAXBURSTLEN & 0xF) << 16
await tb.axi_master.write_dword(DMACH0_S_BASE+0x02C + (ch<<8), data, byteorder='little')
async def AdaSetChSRCTRANSCFG(dut, tb, ch, SRCMEMATTRLO, SRCMEMATTRHI, SRCSHAREATTR, SRCNONSECATTR, SRCPRIVATTR, SRCMAXBURSTLEN):
data = SRCMEMATTRLO & 0x7
data += (SRCMEMATTRHI & 0x7) << 4
data += (SRCSHAREATTR & 0x3) << 8
data += (SRCNONSECATTR & 0x1) << 10
data += (SRCPRIVATTR & 0x1) << 11
data += (SRCMAXBURSTLEN & 0xF) << 16
await tb.axi_master.write_dword(DMACH0_S_BASE+0x028 + (ch<<8), data, byteorder='little')
async def AdaSetChXADDRINC(dut, tb, ch, SRCXADDRINC, DESXADDRINC):
data = SRCXADDRINC & 0xFF
data += (DESXADDRINC & 0xFF) << 16
await tb.axi_master.write_dword(DMACH0_S_BASE+0x030 + (ch<<8), data, byteorder='little')
async def AdaEnable(dut, tb, ch):
CH_CMD = await tb.axi_master.read_dword(DMACH0_S_BASE + (ch<<8))
CH_CMD = CH_CMD ^ 0x1
await tb.axi_master.write_dword(DMACH0_S_BASE + (ch<<8), CH_CMD, byteorder = 'little')
async def AdaGetEnable(dut, tb, ch):
CH_CMD = await tb.axi_master.read_dword(DMACH0_S_BASE + (ch<<8))
return CH_CMD & 0x1
async def AdaGetStatus(dut, tb, ch):
CH_STATUS = await tb.axi_master.read_dword(DMACH0_S_BASE + 0x004 + (ch<<8))
return CH_STATUS
async def AdaSetIntrEn(dut, tb, ch, INTREN_DONE, INTREN_ERR, INTREN_DISABLED, INTREN_STOPPED, INTREN_SRCTRIGINWAIT, INTREN_DESTRIGINWAIT, INTREN_TRIGOUTACKWAIT):
data = INTREN_DONE & 0x1
data += (INTREN_ERR & 0x1) << 1
data += (INTREN_DISABLED & 0x1) << 2
data += (INTREN_STOPPED & 0x1) << 3
data += (INTREN_SRCTRIGINWAIT & 0x1) << 8
data += (INTREN_DESTRIGINWAIT & 0x1) << 9
data += (INTREN_TRIGOUTACKWAIT & 0x1) << 10
await tb.axi_master.write_dword(DMACH0_S_BASE + 0x008 + (ch<<8), data, byteorder='little')
async def AdaGetIntrEn(dut, tb, ch):
return await tb.axi_master.read_dword(DMACH0_S_BASE + 0x008 + (ch<<8))
\ No newline at end of file
from enum import Enum
class TRANSIZE_type(Enum):
Byte = 0
Halfword = 1
Word = 2
DoubleWord = 3
bits128 = 4
bits256 = 5
bits512 = 6
bits1024 = 7
class XYTYPE_type(Enum):
dis = 0
cont = 1
wrap = 2
fill = 3
# Copyright (c) 2020 Alex Forencich
#
# Permission is hereby granted, free of charge, to any person obtaining a copy
# of this software and associated documentation files (the "Software"), to deal
# in the Software without restriction, including without limitation the rights
# to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
# copies of the Software, and to permit persons to whom the Software is
# furnished to do so, subject to the following conditions:
#
# The above copyright notice and this permission notice shall be included in
# all copies or substantial portions of the Software.
#
# THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
# IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY
# FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
# AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
# LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
# OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
# THE SOFTWARE.
TOPLEVEL_LANG = verilog
SIM ?= questa
WAVES ?= 0
GUI ?= 0
COCOTB_HDL_TIMEUNIT = 1ns
COCOTB_HDL_TIMEPRECISION = 1ns
DUT = millisoc_expansion_wrapper
TOPLEVEL = millisoc_expansion_wrapper
MODULE = millisoc_expansion_tests
VERILOG_SOURCES += ../../logical/top_millisoc_expansion/verilog/millisoc_expansion_wrapper.v
ifeq ($(SIM), icarus)
PLUSARGS += -fst
COMPILE_ARGS += $(foreach v,$(filter PARAM_%,$(.VARIABLES)),-P $(TOPLEVEL).$(subst PARAM_,,$(v))=$($(v)))
ifeq ($(WAVES), 1)
VERILOG_SOURCES += iverilog_dump.v
COMPILE_ARGS += -s iverilog_dump
endif
else ifeq ($(SIM), verilator)
COMPILE_ARGS += -Wno-SELRANGE -Wno-WIDTH -Wno-CASEINCOMPLETE
COMPILE_ARGS += $(foreach v,$(filter PARAM_%,$(.VARIABLES)),-G$(subst PARAM_,,$(v))=$($(v)))
ifeq ($(WAVES), 1)
COMPILE_ARGS += --trace-fst
endif
endif
include $(SOCLABS_MILLISOC_EXP_DIR)/flist/millisoc_expansion_cocotb.flist
include $(shell cocotb-config --makefiles)/Makefile.sim
iverilog_dump.v:
echo 'module iverilog_dump();' > $@
echo 'initial begin' >> $@
echo ' $$dumpfile("$(TOPLEVEL).fst");' >> $@
echo ' $$dumpvars(0, $(TOPLEVEL));' >> $@
echo 'end' >> $@
echo 'endmodule' >> $@
clean::
@rm -rf iverilog_dump.v
@rm -rf dump.fst $(TOPLEVEL).fst
This diff is collapsed.
module millisoc_expansion_tb;
endmodule
\ No newline at end of file
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