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Created with Raphaël 2.2.024Jul231116Jan1Dec16Nov1522Sep317Aug914Jul1341Jun18May25Apr2413631Mar1421Jan87425Nov24new top-level fpgabuild.sh and script updates in the style of nanosocmastermasterUpdate the GettingStarter docUpdate the build and simulations enviroment closer to nanosocrepair Arm AAA IP paths for better vesrion independencecorrect a corruption introduced into the build_mcu_fpga_pynq_z2 TCL scriptclean up FPGA build warnings (thanks Meredith) and DMA230 source pathsUpdate README.md to include PL230 DMAUpdate project for latest AAA PL230 DMA controller - simulation and FPGA implementationupgrade design for PL230 Micro DMA with basic integration testupdate the product bundle part numbers to reflect AAA product list updatesupdate v2html doc tree to match RTL updatesadd other Xilinx target technologies to ft1248_to_stream8 IP modulerepair SWD IO mapping, and add clock port waiver to SWDCLK on PMOD interfacepad out start of boot message to fix boot rom with ft1248 interfaceadd local ip_repo with integration components and update associated tcl build scriptsremove server-specific export path from official scriptclean up ip search paths and remove a server-specific path dependencyFix uart address in pz104 notebookFPGA-dev-v2.4FPGA-dev-v2.4upgrade FPGA support for Xilinx PYNQ platform (vivado 2021.1 environment)add the chip_pads layer for testbench tri-state IOsAdd UART2 and FT1248 boot code message support, 20MHz for FPGA, 9600baud serialfpga_imp directory target board example scripts ready for experimental useFPGA-dev-v2.3FPGA-dev-v2.3clean up clock and reset port pad connections and update GLIB dummy power padsupdate testbench to run debug tester from ft1248 outputupdate v2html to match RTL changesrename apb_usrt and clean up connectivityupdate IO library modelsupdate IOPADS, top-level and v2html docupdate v2html tree and mangled boot ROMupdate docs and derived mangled filesNew ADP controller integrated in place of PL230 with testbench supportAdd binary text output file to ROM file generatorcut down Flash and SRAM sizes to still run larger testcode imagesremove HPROT redundant interface portUpdate the new cmsdk_mcu_chip.v level of hierarchy to match cmsdk_mcu.v changesImprove the datestamp in bootrom.v generator to YYMMDDHHMMrebuild ahb_bootrom__mangled to support alternative ROM synthesisreference log files for CPU trace and UART2 addedadded header and date stamp to bootrom.v generatorprogram baudrate for 4800 buad @ 1MHz and update uart capture testbench