clean up clock and reset port pad connections and update GLIB dummy power pads
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- Cortex-M0/soclabs_demo/systems/cortex_m0_mcu/verilog/cmsdk_mcu_chip.v 27 additions, 22 deletions...clabs_demo/systems/cortex_m0_mcu/verilog/cmsdk_mcu_chip.v
- GLIB/pads/verilog/PAD_VDDIO.v 2 additions, 1 deletionGLIB/pads/verilog/PAD_VDDIO.v
- GLIB/pads/verilog/PAD_VDDSOC.v 1 addition, 0 deletionsGLIB/pads/verilog/PAD_VDDSOC.v
- GLIB/pads/verilog/PAD_VSS.v 1 addition, 0 deletionsGLIB/pads/verilog/PAD_VSS.v
- GLIB/pads/verilog/PAD_VSSIO.v 1 addition, 0 deletionsGLIB/pads/verilog/PAD_VSSIO.v
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