clean up FPGA build warnings (thanks Meredith) and DMA230 source paths

Cortex-M0/soclabs_demo/systems/cortex_m0_mcu/fpga_imp/scripts/build_mcu_fpga_ip.tcl

@@ -71,6 +71,8 @@ read_verilog  $soc_vlog/cmsdk_mcu_sysctrl.v
 read_verilog  $soc_vlog/cmsdk_mcu_system.v
 read_verilog  $soc_vlog/cmsdk_mcu_chip.v
 
+set_property top cmsdk_mcu_chip [current_fileset]
+
 # FPGA specific timing constraints
 #read_xdc target_fpga/fpga_timing.xdc
 

Cortex-M0/soclabs_demo/systems/cortex_m0_mcu/fpga_imp/scripts/build_mcu_fpga_pynq_z2.tcl

@@ -78,6 +78,8 @@ set_property file_type {Verilog Header} [get_files  ../../../../../../arm-AAA-ip
 
 add_files $importDir/fpga_pinmap.xdc
 
+vivado -mode tcl -source scripts/build_mcu_fpga_ip.tcl
+
 #
 # STEP#3: save in Project mode to complete flow
 #

Cortex-M0/soclabs_demo/systems/cortex_m0_mcu/fpga_imp/scripts/build_mcu_fpga_pynq_zcu104.tcl

@@ -77,6 +77,8 @@ set_property file_type {Verilog Header} [get_files  ../../../../../../arm-AAA-ip
 
 add_files $importDir/fpga_pinmap.xdc
 
+set_property top design_1_wrapper [current_fileset]
+
 #
 # STEP#3: save in Project mode to complete flow
 #

Cortex-M0/soclabs_demo/systems/cortex_m0_mcu/fpga_imp/scripts/rtl_source_cmsdk.tcl

@@ -16,12 +16,3 @@ read_verilog  [ glob $cmsdk_vlog/logical/cmsdk_ahb_bitband/verilog/*.v ]
 read_verilog  [ glob $cmsdk_vlog/logical/cmsdk_ahb_master_mux/verilog/*.v ]
 read_verilog  $cmsdk_vlog/logical/models/clkgate/cmsdk_clock_gate.v
 read_verilog  $cmsdk_vlog/logical/cmsdk_ahb_to_sram/verilog/cmsdk_ahb_to_sram.v
-
-set search_path [ concat $search_path ../../../../../../arm-AAA-ip/DMA-230_MicroDMA_Controller/PL230-BU-00000-r0p0-02rel2/shared/logical/pl230_udma/verilog ]
-read_verilog  ../verilog/pl230_defs.v
-read_verilog ../../../../../../arm-AAA-ip/DMA-230_MicroDMA_Controller/PL230-BU-00000-r0p0-02rel2/shared/logical/pl230_udma/verilog/pl230_ahb_ctrl.v
-read_verilog ../../../../../../arm-AAA-ip/DMA-230_MicroDMA_Controller/PL230-BU-00000-r0p0-02rel2/shared/logical/pl230_udma/verilog/pl230_apb_regs.v
-read_verilog ../../../../../../arm-AAA-ip/DMA-230_MicroDMA_Controller/PL230-BU-00000-r0p0-02rel2/shared/logical/pl230_udma/verilog/pl230_dma_data.v
-read_verilog ../../../../../../arm-AAA-ip/DMA-230_MicroDMA_Controller/PL230-BU-00000-r0p0-02rel2/shared/logical/pl230_udma/verilog/pl230_udma.v
-read_verilog ../../../../../../arm-AAA-ip/DMA-230_MicroDMA_Controller/PL230-BU-00000-r0p0-02rel2/shared/logical/pl230_udma/verilog/pl230_undefs.v
-