update IOPADS, top-level and v2html doc

88cac616 · dwf1m12 · fce3b86e · 88cac616 · 88cac616 · 88cac616
Commit 88cac616 authored 3 years ago by dwf1m12
--- a/Cortex-M0/soclabs_demo/systems/cortex_m0_mcu/v2html_doc.tgz
+++ b/Cortex-M0/soclabs_demo/systems/cortex_m0_mcu/v2html_doc.tgz
--- a/Cortex-M0/soclabs_demo/systems/cortex_m0_mcu/verilog/cmsdk_mcu_chip.v
+++ b/Cortex-M0/soclabs_demo/systems/cortex_m0_mcu/verilog/cmsdk_mcu_chip.v
@@ -38,8 +38,6 @@

 `include "cmsdk_mcu_defs.v"

-`define SYNTHBOOTROM 1
-
 module cmsdk_mcu_chip #(
  //-----------------------------------------
  // CPU options
@@ -234,17 +232,17 @@ PAD_VDDIO uPAD_VDDIO_1(
   .PAD(VDDIO)
   );

-PAD_VDDIO uPAD_VSSIO_1(
+PAD_VSSIO uPAD_VSSIO_1(
   .PAD(VSSIO)
   );

 // Core power supplies

-PAD_VDDIO uPAD_VDD_1(
+PAD_VDDSOC uPAD_VDD_1(
   .PAD(VDD)
   );

-PAD_VDDIO uPAD_VSS_1(
+PAD_VSS uPAD_VSS_1(
   .PAD(VSS)
   );
 `endif

--- a/Cortex-M0/soclabs_demo/systems/cortex_m0_mcu/verilog/cmsdk_mcu_defs.v
+++ b/Cortex-M0/soclabs_demo/systems/cortex_m0_mcu/verilog/cmsdk_mcu_defs.v
@@ -9,6 +9,11 @@
 // Copyright © 2021, SoC Labs (www.soclabs.org)
 //-----------------------------------------------------------------------------

+`define BEHAVIORAL_PADS
+`define POWER_PINS
+`define SYNTHBOOTROM 1
+
+
 //-----------------------------------------------------------------------------
 // The confidential and proprietary information contained in this file may
 // only be used by a person authorised under and to the extent permitted

--- a/Cortex-M0/soclabs_demo/systems/cortex_m0_mcu/verilog/tb_cmsdk_mcu.v
+++ b/Cortex-M0/soclabs_demo/systems/cortex_m0_mcu/verilog/tb_cmsdk_mcu.v
@@ -47,7 +47,11 @@ module tb_cmsdk_mcu;
  wire [15:0] P0;      // Port 0
  wire [15:0] P1;      // Port 1

-
+  wire        VDDIO;
+  wire        VSSIO;
+  wire        VDD;
+  wire        VSS;
+  
  //Debug tester signals
  wire        nTRST;
  wire        TDI;

--- a/Cortex-M0/soclabs_demo/systems/cortex_m0_mcu/verilog/tbench_M0.vc
+++ b/Cortex-M0/soclabs_demo/systems/cortex_m0_mcu/verilog/tbench_M0.vc
@@ -49,6 +49,7 @@
 ../verilog/tb_cmsdk_mcu.v
 +incdir+../verilog

+// =============   GLIB Generic Library path  =============
 ../../../../../GLIB/pads/verilog/GLIB_PADLIB.v
 ../../../../../GLIB/mem/verilog/SROM_Ax32.v


--- a/Cortex-M0/soclabs_demo/systems/cortex_m0_mcu/verilog/v2html_M0.vc
+++ b/Cortex-M0/soclabs_demo/systems/cortex_m0_mcu/verilog/v2html_M0.vc
@@ -54,6 +54,20 @@
 -y ../../../../../../arm-AAA-ip/Corstone-101_Foundation_IP/BP210-BU-00000-r1p1-00rel0/logical/cmsdk_debug_tester/verilog
 +incdir+../../../../../../arm-AAA-ip/Corstone-101_Foundation_IP/BP210-BU-00000-r1p1-00rel0/logical/cmsdk_debug_tester/verilog

+// =============   GLIB Generic Library path  =============
+../../../../../GLIB/pads/verilog/PAD_INOUT8MA_NOE.v
+../../../../../GLIB/pads/verilog/PAD_VDDIO.v
+../../../../../GLIB/pads/verilog/PAD_VSSIO.v
+../../../../../GLIB/pads/verilog/PAD_VDDSOC.v
+../../../../../GLIB/pads/verilog/PAD_VSS.v
+../../../../../GLIB/mem/verilog/SROM_Ax32.v
+
+// =============   IPLIB soclabs IP Library path  =============
+../../../../../IPLIB/FT1248_streamio_v1_0/ft1248_streamio_v1_0.v
+../../../../../IPLIB/ADPcontrol_v1_0/ADPcontrol_v1_0.v
+../../../../../IPLIB/ADPcontrol_v1_0/ADPmanager.v
+../verilog/cmsdk_apb_uart_streamio.v
+
 // =============    MCU Module search path    =============
 -y ../verilog
 -y ../../../../../../arm-AAA-ip/Corstone-101_Foundation_IP/BP210-BU-00000-r1p1-00rel0/logical/cmsdk_apb_timer/verilog
@@ -78,15 +92,15 @@
 +incdir+../../../../../../arm-AAA-ip/Corstone-101_Foundation_IP/BP210-BU-00000-r1p1-00rel0/logical/cmsdk_apb_watchdog/verilog
 +incdir+../../../../../../arm-AAA-ip/Corstone-101_Foundation_IP/BP210-BU-00000-r1p1-00rel0/logical/models/memories/

-//// Optional PL230 Micro DMA controller - configure in local ../verilog/pl230_defs.v file
-//-y ../../../../../../arm-AAA-ip/DMA-230_MicroDMA_Controller/PL230-BU-00000-r0p0-02rel1/verilog
-+incdir+../../../../../../arm-AAA-ip/DMA-230_MicroDMA_Controller/PL230-BU-00000-r0p0-02rel1/verilog
-../verilog/pl230_defs.v
-../../../../../../arm-AAA-ip/DMA-230_MicroDMA_Controller/PL230-BU-00000-r0p0-02rel1/verilog/pl230_ahb_ctrl.v
-../../../../../../arm-AAA-ip/DMA-230_MicroDMA_Controller/PL230-BU-00000-r0p0-02rel1/verilog/pl230_apb_regs.v
-../../../../../../arm-AAA-ip/DMA-230_MicroDMA_Controller/PL230-BU-00000-r0p0-02rel1/verilog/pl230_dma_data.v
-../../../../../../arm-AAA-ip/DMA-230_MicroDMA_Controller/PL230-BU-00000-r0p0-02rel1/verilog/pl230_udma.v
-../../../../../../arm-AAA-ip/DMA-230_MicroDMA_Controller/PL230-BU-00000-r0p0-02rel1/verilog/pl230_undefs.v
+//  //// Optional PL230 Micro DMA controller - configure in local ../verilog/pl230_defs.v file
+//  //-y ../../../../../../arm-AAA-ip/DMA-230_MicroDMA_Controller/PL230-BU-00000-r0p0-02rel1/verilog
+//  +incdir+../../../../../../arm-AAA-ip/DMA-230_MicroDMA_Controller/PL230-BU-00000-r0p0-02rel1/verilog
+//  ../verilog/pl230_defs.v
+//  ../../../../../../arm-AAA-ip/DMA-230_MicroDMA_Controller/PL230-BU-00000-r0p0-02rel1/verilog/pl230_ahb_ctrl.v
+//  ../../../../../../arm-AAA-ip/DMA-230_MicroDMA_Controller/PL230-BU-00000-r0p0-02rel1/verilog/pl230_apb_regs.v
+//  ../../../../../../arm-AAA-ip/DMA-230_MicroDMA_Controller/PL230-BU-00000-r0p0-02rel1/verilog/pl230_dma_data.v
+//  ../../../../../../arm-AAA-ip/DMA-230_MicroDMA_Controller/PL230-BU-00000-r0p0-02rel1/verilog/pl230_udma.v
+//  ../../../../../../arm-AAA-ip/DMA-230_MicroDMA_Controller/PL230-BU-00000-r0p0-02rel1/verilog/pl230_undefs.v

 // ============= Cortex-M0 Module search path =============
 // guts of core not exposed, periphery only

--- a/GLIB/pads/verilog/PAD_ANALOG.v
+++ b/GLIB/pads/verilog/PAD_ANALOG.v
+// GLIB_PADLIB.v
+//-----------------------------------------------------------------------------
+// The confidential and proprietary information contained in this file may
+// only be used by a person authorised under and to the extent permitted
+// by a subsisting licensing agreement from ARM Limited.
+//
+//            (C) COPYRIGHT 2009-2010 ARM Limited.
+//                ALL RIGHTS RESERVED
+//
+// This entire notice must be reproduced on all copies of this file
+// and copies of this file may only be made by a person if such person is
+// permitted to do so under the terms of a subsisting license agreement
+// from ARM Limited.
+//
+//      Revision            : $Revision: $
+//
+//      Release Information : $ $
+//-----------------------------------------------------------------------------
+
+// VDDISOL
+module PAD_ANALOG (
+   PAD
+   );
+   inout PAD;
+endmodule // PAD_ANALOG
--- a/GLIB/pads/verilog/PAD_INOUT8MA_NOE.v
+++ b/GLIB/pads/verilog/PAD_INOUT8MA_NOE.v
+// GLIB_PADLIB.v
+//-----------------------------------------------------------------------------
+// The confidential and proprietary information contained in this file may
+// only be used by a person authorised under and to the extent permitted
+// by a subsisting licensing agreement from ARM Limited.
+//
+//            (C) COPYRIGHT 2009-2010 ARM Limited.
+//                ALL RIGHTS RESERVED
+//
+// This entire notice must be reproduced on all copies of this file
+// and copies of this file may only be made by a person if such person is
+// permitted to do so under the terms of a subsisting license agreement
+// from ARM Limited.
+//
+//      Revision            : $Revision: $
+//
+//      Release Information : $ $
+//-----------------------------------------------------------------------------
+
+module PAD_INOUT8MA_NOE (
+   // Inouts
+   PAD, 
+   // Outputs
+   O, 
+   // Inputs
+   I,
+   NOE
+   );
+   inout PAD;
+   output I;
+   input O;
+   input NOE;
+
+`ifdef BEHAVIORAL_PADS
+   assign I = PAD;
+   assign PAD = ~NOE ? O : 1'bz; 
+`else
+   bufif1 #2 (PAD, O, ~NOE);
+   buf #1 (I, PAD);
+   always @(PAD)
+     begin
+       if (($countdrivers(PAD) > 1) && (PAD === 1'bx))
+         $display("%t ++BUS CONFLICT++ : %m", $realtime);
+     end
+`endif // ifdef BEHAVIORAL_PADS
+endmodule // PAD_INOUT8MA_NOE
--- a/GLIB/pads/verilog/PAD_INOUT8MA_OE.v
+++ b/GLIB/pads/verilog/PAD_INOUT8MA_OE.v
+// GLIB_PADLIB.v
+//-----------------------------------------------------------------------------
+// The confidential and proprietary information contained in this file may
+// only be used by a person authorised under and to the extent permitted
+// by a subsisting licensing agreement from ARM Limited.
+//
+//            (C) COPYRIGHT 2009-2010 ARM Limited.
+//                ALL RIGHTS RESERVED
+//
+// This entire notice must be reproduced on all copies of this file
+// and copies of this file may only be made by a person if such person is
+// permitted to do so under the terms of a subsisting license agreement
+// from ARM Limited.
+//
+//      Revision            : $Revision: $
+//
+//      Release Information : $ $
+//-----------------------------------------------------------------------------
+
+module PAD_INOUT8MA_OE (
+   // Inouts
+   PAD, 
+   // Outputs
+   O, 
+   // Inputs
+   I,
+   OE
+   );
+   inout PAD;
+   output I;
+   input O;
+   input OE;
+`ifdef BEHAVIORAL_PADS
+   assign I = PAD;
+   assign PAD = OE ? O : 1'bz; 
+`else
+   bufif1 #2 (PAD, O, OE);
+   buf #1 (I, PAD);
+
+   always @(PAD)
+     begin
+       if (($countdrivers(PAD) > 1) && (PAD === 1'bx))
+         $display("%t ++BUS CONFLICT++ : %m", $realtime);
+     end
+`endif // ifdef BEHAVIORAL_PADS
+endmodule // PAD_INOUT8MA_OE
--- a/GLIB/pads/verilog/PAD_VDDIO.v
+++ b/GLIB/pads/verilog/PAD_VDDIO.v
+// GLIB_PADLIB.v
+//-----------------------------------------------------------------------------
+// The confidential and proprietary information contained in this file may
+// only be used by a person authorised under and to the extent permitted
+// by a subsisting licensing agreement from ARM Limited.
+//
+//            (C) COPYRIGHT 2009-2010 ARM Limited.
+//                ALL RIGHTS RESERVED
+//
+// This entire notice must be reproduced on all copies of this file
+// and copies of this file may only be made by a person if such person is
+// permitted to do so under the terms of a subsisting license agreement
+// from ARM Limited.
+//
+//      Revision            : $Revision: $
+//
+//      Release Information : $ $
+//-----------------------------------------------------------------------------
+
+module PAD_VDDIO (
+   PAD
+   );
+   inout PAD;
+endmodule // PAD_VDDIO
--- a/GLIB/pads/verilog/PAD_VDDSOC.v
+++ b/GLIB/pads/verilog/PAD_VDDSOC.v
+// GLIB_PADLIB.v
+//-----------------------------------------------------------------------------
+// The confidential and proprietary information contained in this file may
+// only be used by a person authorised under and to the extent permitted
+// by a subsisting licensing agreement from ARM Limited.
+//
+//            (C) COPYRIGHT 2009-2010 ARM Limited.
+//                ALL RIGHTS RESERVED
+//
+// This entire notice must be reproduced on all copies of this file
+// and copies of this file may only be made by a person if such person is
+// permitted to do so under the terms of a subsisting license agreement
+// from ARM Limited.
+//
+//      Revision            : $Revision: $
+//
+//      Release Information : $ $
+//-----------------------------------------------------------------------------
+
+// core logic supply rails (1V0, 0V)
+module PAD_VDDSOC (
+   PAD
+   );
+   inout PAD;
+endmodule // PAD_VDDSOC
--- a/GLIB/pads/verilog/PAD_VSS.v
+++ b/GLIB/pads/verilog/PAD_VSS.v
+// GLIB_PADLIB.v
+//-----------------------------------------------------------------------------
+// The confidential and proprietary information contained in this file may
+// only be used by a person authorised under and to the extent permitted
+// by a subsisting licensing agreement from ARM Limited.
+//
+//            (C) COPYRIGHT 2009-2010 ARM Limited.
+//                ALL RIGHTS RESERVED
+//
+// This entire notice must be reproduced on all copies of this file
+// and copies of this file may only be made by a person if such person is
+// permitted to do so under the terms of a subsisting license agreement
+// from ARM Limited.
+//
+//      Revision            : $Revision: $
+//
+//      Release Information : $ $
+//-----------------------------------------------------------------------------
+
+module PAD_VSS (
+   PAD
+   );
+   inout PAD;
+endmodule // PAD_VSS
--- a/GLIB/pads/verilog/PAD_VSSIO.v
+++ b/GLIB/pads/verilog/PAD_VSSIO.v
+// GLIB_PADLIB.v
+//-----------------------------------------------------------------------------
+// The confidential and proprietary information contained in this file may
+// only be used by a person authorised under and to the extent permitted
+// by a subsisting licensing agreement from ARM Limited.
+//
+//            (C) COPYRIGHT 2009-2010 ARM Limited.
+//                ALL RIGHTS RESERVED
+//
+// This entire notice must be reproduced on all copies of this file
+// and copies of this file may only be made by a person if such person is
+// permitted to do so under the terms of a subsisting license agreement
+// from ARM Limited.
+//
+//      Revision            : $Revision: $
+//
+//      Release Information : $ $
+//-----------------------------------------------------------------------------
+
+module PAD_VSSIO (
+   PAD
+   );
+   inout PAD;
+endmodule // PAD_VSSIO
+