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Commit 593ff7bb authored by dwf1m12's avatar dwf1m12
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add the chip_pads layer for testbench tri-state IOs

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Cortex-M0/soclabs_demo/systems/cortex_m0_mcu/verilog/cmsdk_mcu_chip_pads.v 0 → 100644
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//-----------------------------------------------------------------------------
// customised top-level example Cortex-M0 controller
// A joint work commissioned on behalf of SoC Labs, under Arm Academic Access license.
//
// Contributors
//
// David Flynn (d.w.flynn@soton.ac.uk)
//
// Copyright 2021-2, SoC Labs (www.soclabs.org)
//-----------------------------------------------------------------------------
//-----------------------------------------------------------------------------
// The confidential and proprietary information contained in this file may
// only be used by a person authorised under and to the extent permitted
// by a subsisting licensing agreement from Arm Limited or its affiliates.
//
// (C) COPYRIGHT 2010-2013 Arm Limited or its affiliates.
// ALL RIGHTS RESERVED
//
// This entire notice must be reproduced on all copies of this file
// and copies of this file may only be made by a person if such person is
// permitted to do so under the terms of a subsisting license agreement
// from Arm Limited or its affiliates.
//
// SVN Information
//
// Checked In : $Date: 2017-10-10 15:55:38 +0100 (Tue, 10 Oct 2017) $
//
// Revision : $Revision: 371321 $
//
// Release Information : Cortex-M System Design Kit-r1p1-00rel0
//
//-----------------------------------------------------------------------------
//-----------------------------------------------------------------------------
// Abstract : Top level for example Cortex-M0/Cortex-M0+ microcontroller
//-----------------------------------------------------------------------------
//
`include "cmsdk_mcu_defs.v"
module cmsdk_mcu_chip_pads (
`ifdef POWER_PINS
inout wire VDDIO,
inout wire VSSIO,
inout wire VDD,
inout wire VSS,
`endif
/// input wire XTAL1, // input
inout wire XTAL1, // input
inout wire XTAL2, // output
/// input wire NRST, // active low reset
inout wire NRST, // active low reset
inout wire [15:0] P0,
inout wire [15:0] P1,
`ifdef ARM_CMSDK_INCLUDE_JTAG
input wire nTRST,
input wire TDI,
output wire TDO,
`endif
inout wire SWDIOTMS,
/// input wire SWCLKTCK);
inout wire SWCLKTCK);
//------------------------------------
// internal wires
wire xtal_clk_i;
wire xtal_clk_o;
wire nrst_i;
wire [15:0] p0_i; // level-shifted input from pad
wire [15:0] p0_o; // output port drive
wire [15:0] p0_e; // active high output drive enable (pad tech dependent)
wire [15:0] p0_z; // active low output drive enable (pad tech dependent)
wire [15:0] p1_i; // level-shifted input from pad
wire [15:0] p1_o; // output port drive
wire [15:0] p1_e; // active high output drive enable (pad tech dependent)
wire [15:0] p1_z; // active low output drive enable (pad tech dependent)
`ifdef ARM_CMSDK_INCLUDE_JTAG
wire ntrst_i;
wire tdi_i;
wire tdo_o;
`endif
wire swdio_i;
wire swdio_o;
wire swdio_e;
wire swdio_z;
wire swdclk_i;
`ifdef ARM_CMSDK_INCLUDE_CLKGATE
parameter CLKGATE_PRESENT = 1;
`else
parameter CLKGATE_PRESENT = 0;
`endif
// Big or Little Endian
// For the changes in the endianness of the system it should be noted that hex file used
// in the instantiation of the cmsdk_debug_tester is also impacted. Therefore the
// following changes are enforced:
//
// BE=0 (LITTLE) -> .ROM_MEMFILE("debugtester_le.hex")
//
// BE=1 (BIG) -> .ROM_MEMFILE("debugtester_be.hex")
parameter BE = 0; // Big or little endian
parameter BKPT = 4; // Number of breakpoint comparators
parameter DBG = 1; // Debug configuration
parameter NUMIRQ = 32; // NUM of IRQ
parameter SMUL = 0; // Multiplier configuration
parameter SYST = 1; // SysTick
parameter WIC = 1; // Wake-up interrupt controller support
parameter WICLINES = 34; // Supported WIC lines
parameter WPT = 2; // Number of DWT comparators
parameter RESET_ALL_REGS = 0; // Do not reset all registers
`ifdef CORTEX_M0PLUS
parameter AWIDTH = 16; // Micro Trace Buffer SRAM address width:
// 5 to 32
parameter BASEADDR = 32'hF0000003; // ROM Table Base Address
`ifdef ARM_CMSDK_INCLUDE_F16
parameter HWF = 1; // Half-Word Fetching
`else
parameter HWF = 0; // Half-Word Fetching
`endif
`ifdef ARM_CMSDK_INCLUDE_IOP
parameter IOP = 1; // IO Port interface selected
`else
parameter IOP = 0; // IO Port not selected
`endif
parameter IRQDIS = 32'h00000000; // Interrupt Disable
parameter MPU = 0; // 8 Memory Protection Regions
`ifdef ARM_CMSDK_INCLUDE_MTB
parameter MTB = 1; // MTB present
`else
parameter MTB = 0; // MTB not present
`endif
parameter USER = 1; // User/Privilege
parameter VTOR = 1; // Vector Table Offset support
`endif
//-----------------------------------------
// Memory options - see cmsdk_mcu_defs.v
// This is defined in systems/cortex_m0_mcu/cmsdk_mcu_defs.v
// Based on the definition constants in logical/models/memories/cmsdk_ahb_memory_model_defs.v
// 0) AHB_ROM_NONE - memory not present
// 1) AHB_ROM_BEH_MODEL - behavioral ROM memory
// 2) AHB_ROM_FPGA_SRAM_MODEL - behavioral FPGA SRAM model with SRAM wrapper
// 3) AHB_ROM_FLASH32_MODEL - behavioral 32-bit flash memory
parameter BOOT_MEM_TYPE = `ARM_CMSDK_BOOT_MEM_TYPE; // Boot loader memory type
// This is defined in systems/cortex_m0_mcu/cmsdk_mcu_defs.v
// Based on the definition constants in logical/models/memories/cmsdk_ahb_memory_model_defs.v
// 0) AHB_ROM_NONE - memory not present (Not valid for a Cortex-M0 system)
// 1) AHB_ROM_BEH_MODEL - behavioral ROM memory
// 2) AHB_ROM_FPGA_SRAM_MODEL - behavioral FPGA SRAM model with SRAM wrapper
// 3) AHB_ROM_FLASH32_MODEL - behavioral 32-bit flash memory
parameter ROM_MEM_TYPE = `ARM_CMSDK_ROM_MEM_TYPE; // ROM memory type
// This is defined in systems/cortex_m0_mcu/cmsdk_mcu_defs.v
// Based on the definition constants in logical/models/memories/cmsdk_ahb_memory_model_defs.v
// 0) AHB_RAM_NONE - memory not present (Not valid for a Cortex-M0 system
// 1) AHB_RAM_BEH_MODEL - behavioral RAM memory
// 2) AHB_RAM_FPGA_SRAM_MODEL - behavioral SRAM model with SRAM wrapper
// 3) AHB_RAM_EXT_SRAM16_MODEL - for benchmarking using 16-bit external asynchronous SRAM
// 4) AHB_RAM_EXT_SRAM8_MODEL - for benchmarking using 8-bit external asynchronous SRAM
parameter RAM_MEM_TYPE = `ARM_CMSDK_RAM_MEM_TYPE; // RAM memory type
//-----------------------------------------
// System options
`ifdef ARM_CMSDK_INCLUDE_BITBAND
parameter INCLUDE_BITBAND = 1;
// Include instantiation of Bit-band wrapper
// This option add bit band wrapper to CPU interface
`else
parameter INCLUDE_BITBAND = 0;
`endif
`ifdef ARM_CMSDK_INCLUDE_DMA
parameter INCLUDE_DMA = 1; // Include instantiation of DMA-230
// This option also add a number of bus components
`else
parameter INCLUDE_DMA = 0;
`endif
`ifdef ARM_CMSDK_INCLUDE_JTAG
parameter INCLUDE_JTAG = 1; // Include JTAG feature
`else
parameter INCLUDE_JTAG = 0; // Do not Include JTAG feature
`endif
// --------------------------------------------------------------------------------
// Cortex-M0/Cortex-M0+ Microcontroller
// --------------------------------------------------------------------------------
cmsdk_mcu_chip
// cmsdk_mcu
#(.CLKGATE_PRESENT (CLKGATE_PRESENT),
.BE (BE),
.BKPT (BKPT), // Number of breakpoint comparators
.DBG (DBG), // Debug configuration
.NUMIRQ (NUMIRQ), // NUMIRQ
.SMUL (SMUL), // Multiplier configuration
.SYST (SYST), // SysTick
.WIC (WIC), // Wake-up interrupt controller support
.WICLINES (WICLINES), // Supported WIC lines
`ifdef CORTEX_M0PLUS
.AWIDTH (AWIDTH), // Micro Trace Buffer SRAM address width
.BASEADDR (BASEADDR), // ROM Table Base Address
.HWF (HWF), // Half Word Fetching
.IOP (IOP), // IO Port interface selected
.IRQDIS (IRQDIS), // Interrupt Disable
.MPU (MPU), // Memory Protection support
.MTB (MTB), // MTB select
.USER (USER), // User/Privilege
.VTOR (VTOR), // Vector Table Offset support
`endif
.WPT (WPT), // Number of DWT comparators
.RESET_ALL_REGS (RESET_ALL_REGS), // Do not reset all registers
.BOOT_MEM_TYPE (BOOT_MEM_TYPE), // Boot loader memory type
.ROM_MEM_TYPE (ROM_MEM_TYPE), // ROM memory type
.RAM_MEM_TYPE (RAM_MEM_TYPE), // RAM loader memory type
.INCLUDE_BITBAND (INCLUDE_BITBAND), // Include bit band wrapper
.INCLUDE_DMA (INCLUDE_DMA), // Include DMA feature
.INCLUDE_JTAG (INCLUDE_JTAG) // Include JTAG feature
)
u_cmsdk_mcu (
`ifdef POWER_PINS
.VDDIO (VDDIO),
.VSSIO (VSSIO),
.VDD (VDD),
.VSS (VSS),
`endif
.xtal_clk_i(xtal_clk_i),
.xtal_clk_o(xtal_clk_o),
.nrst_i(nrst_i),
.p0_i(p0_i), // level-shifted input from pad
.p0_o(p0_o), // output port drive
.p0_e(p0_e), // active high output drive enable (pad tech dependent)
.p0_z(p0_z), // active low output drive enable (pad tech dependent)
.p1_i(p1_i), // level-shifted input from pad
.p1_o(p1_o), // output port drive
.p1_e(p1_e), // active high output drive enable (pad tech dependent)
.p1_z(p1_z), // active low output drive enable (pad tech dependent)
`ifdef ARM_CMSDK_INCLUDE_JTAG
.ntrst_i(ntrst_i),
.tdi_i(tdi_i),
.tdo_o(tdo_o),
`endif
.swdio_i(swdio_i),
.swdio_o(swdio_o),
.swdio_e(swdio_e),
.swdio_z(swdio_z),
.swdclk_i(swdclk_i)
);
//TIE_HI uTIEHI (.tiehi(tiehi));
wire tiehi = 1'b1;
//TIE_LO uTIELO (.tielo(tielo));
wire tielo = 1'b0;
// --------------------------------------------------------------------------------
// IO pad (GLIB Generic Library napping)
// --------------------------------------------------------------------------------
`ifdef POWER_PINS
// Pad IO power supplies
PAD_VDDIO uPAD_VDDIO_1(
.PAD(VDDIO)
);
PAD_VSSIO uPAD_VSSIO_1(
.PAD(VSSIO)
);
// Core power supplies
PAD_VDDSOC uPAD_VDD_1(
.PAD(VDD)
);
PAD_VSS uPAD_VSS_1(
.PAD(VSS)
);
`endif
// Clock, Reset and Serial Wire Debug ports
PAD_INOUT8MA_NOE uPAD_XTAL_I (
.PAD (XTAL1),
.O (tielo),
.I (xtal_clk_i),
.NOE (tiehi)
);
PAD_INOUT8MA_NOE uPAD_XTAL_O (
.PAD (XTAL2),
.O (xtal_clk_o),
.I ( ),
.NOE (tielo)
);
PAD_INOUT8MA_NOE uPAD_NRST_I (
.PAD (NRST),
.O (tielo),
.I (nrst_i),
.NOE (tiehi)
);
PAD_INOUT8MA_NOE uPAD_SWDIO_I (
.PAD (SWDIOTMS),
.O (swdio_o),
.I (swdio_i),
.NOE (swdio_z)
);
PAD_INOUT8MA_NOE uPAD_SWDCLK_I (
.PAD (SWCLKTCK),
.O (tielo),
.I (swdclk_i),
.NOE (tiehi)
);
// GPI.I Port 0 x 16
PAD_INOUT8MA_NOE uPAD_P0_00 (
.PAD (P0[00]),
.O (p0_o[00]),
.I (p0_i[00]),
.NOE (p0_z[00])
);
PAD_INOUT8MA_NOE uPAD_P0_01 (
.PAD (P0[01]),
.O (p0_o[01]),
.I (p0_i[01]),
.NOE (p0_z[01])
);
PAD_INOUT8MA_NOE uPAD_P0_02 (
.PAD (P0[02]),
.O (p0_o[02]),
.I (p0_i[02]),
.NOE (p0_z[02])
);
PAD_INOUT8MA_NOE uPAD_P0_03 (
.PAD (P0[03]),
.O (p0_o[03]),
.I (p0_i[03]),
.NOE (p0_z[03])
);
PAD_INOUT8MA_NOE uPAD_P0_04 (
.PAD (P0[04]),
.O (p0_o[04]),
.I (p0_i[04]),
.NOE (p0_z[04])
);
PAD_INOUT8MA_NOE uPAD_P0_05 (
.PAD (P0[05]),
.O (p0_o[05]),
.I (p0_i[05]),
.NOE (p0_z[05])
);
PAD_INOUT8MA_NOE uPAD_P0_06 (
.PAD (P0[06]),
.O (p0_o[06]),
.I (p0_i[06]),
.NOE (p0_z[06])
);
PAD_INOUT8MA_NOE uPAD_P0_07 (
.PAD (P0[07]),
.O (p0_o[07]),
.I (p0_i[07]),
.NOE (p0_z[07])
);
PAD_INOUT8MA_NOE uPAD_P0_08 (
.PAD (P0[08]),
.O (p0_o[08]),
.I (p0_i[08]),
.NOE (p0_z[08])
);
PAD_INOUT8MA_NOE uPAD_P0_09 (
.PAD (P0[09]),
.O (p0_o[09]),
.I (p0_i[09]),
.NOE (p0_z[09])
);
PAD_INOUT8MA_NOE uPAD_P0_10 (
.PAD (P0[10]),
.O (p0_o[10]),
.I (p0_i[10]),
.NOE (p0_z[10])
);
PAD_INOUT8MA_NOE uPAD_P0_11 (
.PAD (P0[11]),
.O (p0_o[11]),
.I (p0_i[11]),
.NOE (p0_z[11])
);
PAD_INOUT8MA_NOE uPAD_P0_12 (
.PAD (P0[12]),
.O (p0_o[12]),
.I (p0_i[12]),
.NOE (p0_z[12])
);
PAD_INOUT8MA_NOE uPAD_P0_13 (
.PAD (P0[13]),
.O (p0_o[13]),
.I (p0_i[13]),
.NOE (p0_z[13])
);
PAD_INOUT8MA_NOE uPAD_P0_14 (
.PAD (P0[14]),
.O (p0_o[14]),
.I (p0_i[14]),
.NOE (p0_z[14])
);
PAD_INOUT8MA_NOE uPAD_P0_15 (
.PAD (P0[15]),
.O (p0_o[15]),
.I (p0_i[15]),
.NOE (p0_z[15])
);
// GPI.I Port 1 x 16
PAD_INOUT8MA_NOE uPAD_P1_00 (
.PAD (P1[00]),
.O (p1_o[00]),
.I (p1_i[00]),
.NOE (p1_z[00])
);
PAD_INOUT8MA_NOE uPAD_P1_01 (
.PAD (P1[01]),
.O (p1_o[01]),
.I (p1_i[01]),
.NOE (p1_z[01])
);
PAD_INOUT8MA_NOE uPAD_P1_02 (
.PAD (P1[02]),
.O (p1_o[02]),
.I (p1_i[02]),
.NOE (p1_z[02])
);
PAD_INOUT8MA_NOE uPAD_P1_03 (
.PAD (P1[03]),
.O (p1_o[03]),
.I (p1_i[03]),
.NOE (p1_z[03])
);
PAD_INOUT8MA_NOE uPAD_P1_04 (
.PAD (P1[04]),
.O (p1_o[04]),
.I (p1_i[04]),
.NOE (p1_z[04])
);
PAD_INOUT8MA_NOE uPAD_P1_05 (
.PAD (P1[05]),
.O (p1_o[05]),
.I (p1_i[05]),
.NOE (p1_z[05])
);
PAD_INOUT8MA_NOE uPAD_P1_06 (
.PAD (P1[06]),
.O (p1_o[06]),
.I (p1_i[06]),
.NOE (p1_z[06])
);
PAD_INOUT8MA_NOE uPAD_P1_07 (
.PAD (P1[07]),
.O (p1_o[07]),
.I (p1_i[07]),
.NOE (p1_z[07])
);
PAD_INOUT8MA_NOE uPAD_P1_08 (
.PAD (P1[08]),
.O (p1_o[08]),
.I (p1_i[08]),
.NOE (p1_z[08])
);
PAD_INOUT8MA_NOE uPAD_P1_09 (
.PAD (P1[09]),
.O (p1_o[09]),
.I (p1_i[09]),
.NOE (p1_z[09])
);
PAD_INOUT8MA_NOE uPAD_P1_10 (
.PAD (P1[10]),
.O (p1_o[10]),
.I (p1_i[10]),
.NOE (p1_z[10])
);
PAD_INOUT8MA_NOE uPAD_P1_11 (
.PAD (P1[11]),
.O (p1_o[11]),
.I (p1_i[11]),
.NOE (p1_z[11])
);
PAD_INOUT8MA_NOE uPAD_P1_12 (
.PAD (P1[12]),
.O (p1_o[12]),
.I (p1_i[12]),
.NOE (p1_z[12])
);
PAD_INOUT8MA_NOE uPAD_P1_13 (
.PAD (P1[13]),
.O (p1_o[13]),
.I (p1_i[13]),
.NOE (p1_z[13])
);
PAD_INOUT8MA_NOE uPAD_P1_14 (
.PAD (P1[14]),
.O (p1_o[14]),
.I (p1_i[14]),
.NOE (p1_z[14])
);
PAD_INOUT8MA_NOE uPAD_P1_15 (
.PAD (P1[15]),
.O (p1_o[15]),
.I (p1_i[15]),
.NOE (p1_z[15])
);
endmodule
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