Skip to content
Snippets Groups Projects
Commit 1ee0a88f authored by dwf1m12's avatar dwf1m12
Browse files

clean up ip search paths and remove a server-specific path dependency

parent 8a9d2760
No related branches found
No related tags found
No related merge requests found
...@@ -78,7 +78,7 @@ read_verilog $soc_vlog/cmsdk_mcu_chip.v ...@@ -78,7 +78,7 @@ read_verilog $soc_vlog/cmsdk_mcu_chip.v
update_compile_order -fileset sources_1 update_compile_order -fileset sources_1
set mculib_ip ../../../../../MCULIB set mculib_ip ./MCULIB
ipx::package_project -root_dir $mculib_ip -vendor soclabs.org -library user -taxonomy /UserIP -import_files -set_current false -force ipx::package_project -root_dir $mculib_ip -vendor soclabs.org -library user -taxonomy /UserIP -import_files -set_current false -force
...@@ -101,13 +101,6 @@ ipx::archive_core $mculib_ip/soclabs.org_user_cmsdk_mcu_chip_1.0.zip [ipx::curr ...@@ -101,13 +101,6 @@ ipx::archive_core $mculib_ip/soclabs.org_user_cmsdk_mcu_chip_1.0.zip [ipx::curr
ipx::move_temp_component_back -component [ipx::current_core] ipx::move_temp_component_back -component [ipx::current_core]
close_project -delete close_project -delete
#set_property ip_repo_paths {/home/dwf1m12/soclabs/fpga/vivado/pynq/ip_repo /home/dwf1m12/soclabs_git/soclabs-cortexm0-mcu/MCULIB} [current_project] set_property ip_repo_paths { ip_repo ./MCULIB} [current_project]
set_property ip_repo_paths {/home/dwf1m12/soclabs/fpga/vivado/pynq/ip_repo ../../../../../MCULIB} [current_project]
update_ip_catalog update_ip_catalog
close_project close_project
#create_project project_2 /home/dwf1m12/soclabs_git/soclabs-cortexm0-mcu/Cortex-M0/soclabs_demo/systems/cortex_m0_mcu/fpga_imp/project_2 -part xczu7ev-ffvc1156-2-e
#set_property board_part xilinx.com:zcu104:part0:1.1 [current_project]
#set_property coreContainer.enable 1 [current_project]
#set_property ip_repo_paths /home/dwf1m12/soclabs/fpga/vivado/pynq/ip_repo [current_project]
#update_ip_catalog
...@@ -35,15 +35,20 @@ set_part $xilinx_part ...@@ -35,15 +35,20 @@ set_part $xilinx_part
set_property TARGET_LANGUAGE Verilog [current_project] set_property TARGET_LANGUAGE Verilog [current_project]
set_property DEFAULT_LIB work [current_project] set_property DEFAULT_LIB work [current_project]
##set paths [list \
## "../../../../../../../soclabs/fpga/vivado/pynq/ip_repo"\
## "./MCULIB"\
## ]
set paths [list \ set paths [list \
"../../../../../../../soclabs/fpga/vivado/pynq/ip_repo"\ "./MCULIB"\
"../../../../../MCULIB"\
] ]
# Set IP repository paths # Set IP repository paths
set obj [get_filesets sources_1] set obj [get_filesets sources_1]
if { $obj != {} } { if { $obj != {} } {
set_property "ip_repo_paths" "[file normalize "../../../../../../../soclabs/fpga/vivado/pynq/ip_repo"] [file normalize "../../../../../MCULIB"]" $obj ## set_property "ip_repo_paths" "[file normalize "../../../../../../../soclabs/fpga/vivado/pynq/ip_repo"] [file normalize "./MCULIB"]" $obj
set_property "ip_repo_paths" "[file normalize "./MCULIB"]" $obj
# Rebuild user ip_repo's index before adding any source files # Rebuild user ip_repo's index before adding any source files
update_ip_catalog -rebuild update_ip_catalog -rebuild
......
0% Loading or .
You are about to add 0 people to the discussion. Proceed with caution.
Finish editing this message first!
Please register or to comment