rename apb_usrt and clean up connectivity

Cortex-M0/soclabs_demo/systems/cortex_m0_mcu/verilog/cmsdk_apb_uart_streamio.v → Cortex-M0/soclabs_demo/systems/cortex_m0_mcu/verilog/cmsdk_apb_usrt.v

@@ -61,7 +61,7 @@
 // 0x3E0 - 0x3FC  ID registers
 //-------------------------------------
 
-module cmsdk_apb_uart_streamio (
+module cmsdk_apb_usrt (
 // --------------------------------------------------------------------------
 // Port Definitions
 // --------------------------------------------------------------------------
@@ -81,11 +81,6 @@ module cmsdk_apb_uart_streamio (
   output wire        PREADY,   // Device ready
   output wire        PSLVERR,  // Device error response
 
-  input  wire        RXD,      // Serial input
-  output wire        TXD,      // Transmit data output
-  output wire        TXEN,     // Transmit enabled
-  output wire        BAUDTICK, // Baud rate (x16) Tick
-  
   output wire        TX_VALID_o,
   output wire [7:0]  TX_DATA8_o,
   input  wire        TX_READY_i,
@@ -114,6 +109,13 @@ localparam  ARM_CMSDK_APB_UART_CID1 = 8'hF0;
 localparam  ARM_CMSDK_APB_UART_CID2 = 8'h05;
 localparam  ARM_CMSDK_APB_UART_CID3 = 8'hB1;
 
+// original external IOs
+wire        RXD = 1'b1; // Serial input
+wire        TXD;      // Transmit data output
+wire        TXEN;     // Transmit enabled
+wire        BAUDTICK; // Baud rate (x16) Tick
+  
+
   // --------------------------------------------------------------------------
   // Internal wires
   // --------------------------------------------------------------------------

Cortex-M0/soclabs_demo/systems/cortex_m0_mcu/verilog/cmsdk_mcu_chip.v

@@ -974,7 +974,7 @@ assign ADPRESETREQ = adp_gpo8[0];
     .ahb_hwdata        (dmac_hwdata)
   );
 
-   cmsdk_apb_uart_streamio u_apb_uart_com (
+   cmsdk_apb_usrt u_apb_usrt_com (
     .PCLK              (PCLK),     // Peripheral clock
     .PCLKG             (PCLKG),    // Gated PCLK for bus
     .PRESETn           (PRESETn),  // Reset
@@ -991,13 +991,6 @@ assign ADPRESETREQ = adp_gpo8[0];
 
     .ECOREVNUM         (4'h0),// Engineering-change-order revision bits
 
-    .RXD               (1'b1),      // Receive data
-
-    .TXD               ( ),      // Transmit data
-    .TXEN              ( ),     // Transmit Enabled
-
-    .BAUDTICK          ( ),   // Baud rate x16 tick output (for testing)
-
     .TX_VALID_o        (stdio_rx_valid),
     .TX_DATA8_o        (stdio_rx_data8),
     .TX_READY_i        (stdio_rx_ready),

Cortex-M0/soclabs_demo/systems/cortex_m0_mcu/verilog/tbench_M0.vc

@@ -100,7 +100,7 @@
 ../../../../../IPLIB/FT1248_streamio_v1_0/ft1248_streamio_v1_0.v
 ../../../../../IPLIB/ADPcontrol_v1_0/ADPcontrol_v1_0.v
 ../../../../../IPLIB/ADPcontrol_v1_0/ADPmanager.v
-../verilog/cmsdk_apb_uart_streamio.v
+../verilog/cmsdk_apb_usrt.v
 
 // ============= Cortex-M0 Module search path =============