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test_axi.py

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  • test_axi.py 8.78 KiB
    """
    
    Copyright (c) 2020 Alex Forencich
    
    Permission is hereby granted, free of charge, to any person obtaining a copy
    of this software and associated documentation files (the "Software"), to deal
    in the Software without restriction, including without limitation the rights
    to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
    copies of the Software, and to permit persons to whom the Software is
    furnished to do so, subject to the following conditions:
    
    The above copyright notice and this permission notice shall be included in
    all copies or substantial portions of the Software.
    
    THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
    IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY
    FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
    AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
    LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
    OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
    THE SOFTWARE.
    
    """
    
    import itertools
    import logging
    import os
    from numpy import random
    #import cocotb_test.simulator
    #import pytest
    
    import cocotb
    from cocotb.clock import Clock
    from cocotb.triggers import RisingEdge, Timer
    from cocotb.regression import TestFactory
    
    from cocotbext.axi import AxiBus, AxiMaster, AxiBurstType
    import apb
    
    class TB:
        def __init__(self, dut):
            self.dut = dut
    
            self.log = logging.getLogger("cocotb.tb")
            self.log.setLevel(logging.DEBUG)
    
            cocotb.start_soon(Clock(dut.clk, 2, units="ns").start())
            self.apb_master = apb.APBMasterDriver(dut, "APB", dut.clk)
            print(AxiBus.from_prefix(dut, "axi"))
            print(AxiBus.from_prefix(dut, "axi").write)
            self.axi_master = AxiMaster(AxiBus.from_prefix(dut, "axi"), dut.clk, dut.rst, reset_active_level=False)
            self.log.info(self.apb_master)
    
        def set_idle_generator(self, generator=None):
            if generator:
                self.axi_master.write_if.aw_channel.set_pause_generator(generator())
                self.axi_master.write_if.w_channel.set_pause_generator(generator())
                self.axi_master.read_if.ar_channel.set_pause_generator(generator())
    
        def set_backpressure_generator(self, generator=None):
            if generator:
                self.axi_master.write_if.b_channel.set_pause_generator(generator())
                self.axi_master.read_if.r_channel.set_pause_generator(generator())
    
        async def cycle_reset(self):
            self.dut.rst.setimmediatevalue(1)
            await RisingEdge(self.dut.clk)
            await RisingEdge(self.dut.clk)
            self.dut.rst.value = 0
            await RisingEdge(self.dut.clk)
            await RisingEdge(self.dut.clk)
            self.dut.rst.value = 1
            await RisingEdge(self.dut.clk)
            await RisingEdge(self.dut.clk)
    
        async def delay(self, cycle):
            for i in range(cycle):
                await RisingEdge(self.dut.clk)
    
    async def write_read(dut, tb, base_addr, byte_lanes, size):
        for length in list(range(1, byte_lanes*2))+[1024]:
            for offset in list(range(byte_lanes))+list(range(2048-byte_lanes, 2048)):
                tb.log.info("length %d, offset %d", length, offset)
                addr = offset+base_addr
                test_data = bytearray([x % 256 for x in range(length)])
    
                await tb.axi_master.write(addr, test_data, size=size)
    
                data = await tb.axi_master.read(addr, length, size=size)
    
                assert data.data == test_data
    
        await RisingEdge(dut.clk)
        await RisingEdge(dut.clk)
    
    @cocotb.test()
    async def run_test_write_read(dut, idle_inserter=None, backpressure_inserter=None, size=None):
    
        tb = TB(dut)
        
        byte_lanes = tb.axi_master.write_if.byte_lanes
        max_burst_size = tb.axi_master.write_if.max_burst_size
    
        if size is None:
            size = max_burst_size
    
        await tb.cycle_reset()
    
        tb.set_idle_generator(idle_inserter)
        tb.set_backpressure_generator(backpressure_inserter)
    
        await write_read(dut, tb, 0x00000000, byte_lanes, size)
        await write_read(dut, tb, 0x08000000, byte_lanes, size)
        await write_read(dut, tb, 0x10000000, byte_lanes, size)
        await write_read(dut, tb, 0x18000000, byte_lanes, size)
    
    @cocotb.test()
    async def run_dma_1D_test(dut,idle_inserter=None, backpressure_inserter=None, size=None):
    
        tb = TB(dut)
        src_addr    = 0x00000000
        dest_addr   = 0x18000000
        transfer_size = 0x00FF
    
        max_burst_size = tb.axi_master.write_if.max_burst_size
    
        if size is None:
            size = max_burst_size
    
        await tb.cycle_reset()
    
        # Write random data to source address
        for offset in range(0, transfer_size*8, 8):
            addr = src_addr + offset
            test_data = random.bytes(8)
    
            await tb.axi_master.write(addr, test_data, size=size)
            
    
        await RisingEdge(dut.clk)
        await RisingEdge(dut.clk)
        tb.log.info("Start DMA setup")
        await tb.apb_master.busy_send(apb.APBTransaction(0x1010,0x00000000)) #Set source Address 
        await tb.apb_master.busy_send(apb.APBTransaction(0x1018,0x18000000)) #Set Destination address
        await tb.apb_master.busy_send(apb.APBTransaction(0x1020,0x00FF00FF)) #Set Source and destination size
        await tb.apb_master.busy_send(apb.APBTransaction(0x100C,0x000F02F3)) #Config bits 0 001 111 0 000 001 0 1111 0 011 
        await tb.apb_master.busy_send(apb.APBTransaction(0x102C,0x000F0444)) #Dest trans config
        await tb.apb_master.busy_send(apb.APBTransaction(0x1028,0x000F0444))
        await tb.apb_master.busy_send(apb.APBTransaction(0x1030,0x00010001))
        tb.log.info("Finish DMA setup")
        await tb.apb_master.busy_send(apb.APBTransaction(0x1000,0x00000001))
        tstart=cocotb.utils.get_sim_time('ns')
        await tb.delay(20)
        j=0
        while dut.dma_active==1:
            await tb.delay(100)
            j+=1
            if j>20:
                break
        status = apb.APBTransaction(0x1004)
        await tb.apb_master.busy_send(status)
        tb.log.info(status)
        tb.log.info(status.data)
    
        
        tend = cocotb.utils.get_sim_time('ns')
    
    
        for offset in range(0, transfer_size*8, 8):
            src_data = await tb.axi_master.read(src_addr+offset, 8, size=size)
            dest_data = await tb.axi_master.read(dest_addr+offset, 8, size=size)
            assert src_data.data == dest_data.data
        await RisingEdge(dut.clk)
        await RisingEdge(dut.clk)
    
        n_cycles = (tend-tstart)/(2*255)
        tb.log.info("Average no of clocks per transaction = " + str(n_cycles))
        bandwidth = 64*255/(tend-tstart)
        tb.log.info("Bandwidth of DMA transfer = " + str(bandwidth) + " Gbps")
    
    @cocotb.test()
    async def run_dma_1D_axis_test(dut,idle_inserter=None, backpressure_inserter=None, size=None):
        tb = TB(dut)
        src_addr    = 0x00000100
        dest_addr   = 0x18000100
        transfer_size = 0x00FF
    
        max_burst_size = tb.axi_master.write_if.max_burst_size
    
        if size is None:
            size = max_burst_size
    
        await tb.cycle_reset()
    
        # Write random data to source address
        for offset in range(0, transfer_size*8, 8):
            addr = src_addr + offset
            test_data = random.bytes(8)
    
            await tb.axi_master.write(addr, test_data, size=size)
            
    
        await RisingEdge(dut.clk)
        await RisingEdge(dut.clk)
        tb.log.info("Start DMA setup")
        await tb.apb_master.busy_send(apb.APBTransaction(0x1010,0x00000100)) #Set source Address 
        await tb.apb_master.busy_send(apb.APBTransaction(0x1018,0x18000100)) #Set Destination address
        await tb.apb_master.busy_send(apb.APBTransaction(0x1020,0x00FF00FF)) #Set Source and destination size
        await tb.apb_master.busy_send(apb.APBTransaction(0x100C,0x200F02F3)) #Config bits 0010 1000 0000 1111 0000 0010 1111 0011 
        await tb.apb_master.busy_send(apb.APBTransaction(0x102C,0x000F0444)) #Dest trans config
        await tb.apb_master.busy_send(apb.APBTransaction(0x1028,0x000F0444))
        await tb.apb_master.busy_send(apb.APBTransaction(0x1030,0x00010001))
        await tb.apb_master.busy_send(apb.APBTransaction(0x1068,0x00000000))
        tb.log.info("Finish DMA setup")
        await tb.apb_master.busy_send(apb.APBTransaction(0x1000,0x00000001))
        tstart=cocotb.utils.get_sim_time('ns')
        await tb.delay(20)
        j=0
        while dut.dma_active==1:
            await tb.delay(100)
            j+=1
            if j>20:
                break
        status = apb.APBTransaction(0x1004)
        await tb.apb_master.busy_send(status)
        tb.log.info(status)
        tb.log.info(status.data)
    
        
        tend = cocotb.utils.get_sim_time('ns')
    
    
        for offset in range(0, transfer_size*8, 8):
            src_data = await tb.axi_master.read(src_addr+offset, 8, size=size)
            dest_data = await tb.axi_master.read(dest_addr+offset, 8, size=size)
            assert src_data.data == dest_data.data
        await RisingEdge(dut.clk)
        await RisingEdge(dut.clk)
    
        n_cycles = (tend-tstart)/(2*255)
        tb.log.info("Average no of clocks per transaction = " + str(n_cycles))
        bandwidth = 64*255/(tend-tstart)
        tb.log.info("Bandwidth of DMA transfer = " + str(bandwidth) + " Gbps")