invert GWEN and WEN signalling for Arm RegFiles

sram/verilog/sl_sram.v

@@ -32,12 +32,17 @@ module sl_sram #(
   output wire [31:0]   RDATA
   );
 
-localparam TIE_EMA = 3'b010;
-localparam TIE_EMAW = 2'b00;
-wire       GWEN = (&WREN);
-wire  [31:0] WEN;
-assign WEN = ({{8{WREN[3]}},{8{WREN[2]}},{8{WREN[1]}},{8{WREN[0]}}});
-localparam TIE_RET1N = 1'b1;
+// fixed pre-compiled 16K instance supported
+localparam  TIE_EMA = 3'b010;
+localparam  TIE_EMAW = 2'b00;
+wire [11:0] ADDR12 = ADDR;
+wire [31:0] WDATA32 = WDATA;
+wire [31:0] RDATA32;
+assign      RDATA = RDATA32;
+wire        CEN = !CS;
+wire        GWEN = &(~WREN);
+wire [31:0] WEN32 = { {8{!WREN[3]}},{8{!WREN[2]}},{8{!WREN[1]}},{8{!WREN[0]}} };
+localparam  TIE_RET1N = 1'b1;
 
   rf_sp_hdf
     u_rf_sp_hdf (
@@ -45,15 +50,15 @@ localparam TIE_RET1N = 1'b1;
     .VDD (VDD),
     .VSS  (VSS),
 `endif
-    .Q (RDATA),
-    .CLK (CLK),
-    .CEN (!CS),
-    .WEN (WEN),
-    .A (ADDR),
-    .D (WDATA),
-    .EMA (TIE_EMA),
-    .EMAW (TIE_EMAW),
-    .GWEN (GWEN),
+    .Q     (RDATA32),
+    .CLK   (HCLK),
+    .CEN   (CEN),
+    .WEN   (WEN32),
+    .A     (ADDR12),
+    .D     (WDATA32),
+    .EMA   (TIE_EMA),
+    .EMAW  (TIE_EMAW),
+    .GWEN  (GWEN),
     .RET1N (TIE_RET1N)
    );