Add Power Pins

flist/asic_lib_mem_ip.flist

@@ -20,4 +20,5 @@
 
 // - Top-level testbench
 $(SOCLABS_ASIC_LIB_TECH_DIR)/sram/verilog/sl_ahb_sram.v
-$(SOCLABS_ASIC_LIB_TECH_DIR)/rom/verilog/sl_ahb_rom.v
\ No newline at end of file
+$(SOCLABS_ASIC_LIB_TECH_DIR)/rom/verilog/sl_ahb_rom.v
+$(SOCLABS_ASIC_LIB_TECH_DIR)/sram/verilog/sl_sram.v

sram/verilog/sl_ahb_sram.v

@@ -16,6 +16,13 @@ module sl_ahb_sram #(
     parameter RAM_ADDR_W = 14,  // Size of SRAM
     parameter RAM_DATA_W = 32   // Data Width of RAM
 )(
+    `ifdef POWER_PINS
+    inout  wire          VDDCE,
+    inout  wire          VDDPE,
+    inout  wire          VSSE,
+    inout  wire          VDD,
+    inout  wire          VSS,
+    `endif
     // --------------------------------------------------------------------------
     // Port Definitions
     // --------------------------------------------------------------------------
@@ -74,6 +81,11 @@ module sl_ahb_sram #(
     sl_sram #(
         .AW (RAM_ADDR_W)
     ) u_sram (
+        `ifdef POWER_PINS
+        .VDDCE (VDDCE),
+        .VDDPE (VDDPE),
+        .VSSE  (VSSE),
+        `endif
         // SRAM Inputs
         .CLK        (HCLK),
         .ADDR       (addr),

sram/verilog/sl_sram.v

@@ -5,6 +5,11 @@ module sl_sram #(
   parameter AW = 16
  )
  (
+  `ifdef POWER_PINS
+  inout  wire          VDDCE,
+  inout  wire          VDDPE,
+  inout  wire          VSSE,
+  `endif
   // Inputs
   input  wire          CLK,
   input  wire [AW-1:2] ADDR,
@@ -26,9 +31,9 @@ localparam TIE_RET1N = 1'b1;
   rf_sp_hdf
     u_rf_sp_hdf (
 `ifdef POWER_PINS
-    .VDDCE (1'b1),
-    .VDDPE (1'b1),
-    .VSSE  (1'b0),
+    .VDDCE (VDDCE),
+    .VDDPE (VDDPE),
+    .VSSE  (VSSE),
 `endif
     .Q (RDATA),
     .CLK (CLK),