Skip to content
Snippets Groups Projects
Commit f9f935b5 authored by dwn1c21's avatar dwn1c21
Browse files

Initial FPGA wrapper

parent bd0c4aa7
No related branches found
No related tags found
No related merge requests found
Hide whitespace changes
Inline Side-by-side
fpga/pynq_z2/PYNQ-Z2 v1.0.xdc 0 → 100644
+ 210
− 0
View file @ f9f935b5
set_property -dict {PACKAGE_PIN Y18 IOSTANDARD LVCMOS33} [get_ports QSPI_nCS_0]
set_property -dict {PACKAGE_PIN Y19 IOSTANDARD LVCMOS33} [get_ports {QSPI_IO_0[0]}]
set_property -dict {PACKAGE_PIN Y16 IOSTANDARD LVCMOS33} [get_ports {QSPI_IO_0[1]}]
set_property -dict {PACKAGE_PIN Y17 IOSTANDARD LVCMOS33} [get_ports QSPI_SCLK_0]
set_property -dict {PACKAGE_PIN U19 IOSTANDARD LVCMOS33} [get_ports RESET]
set_property -dict {PACKAGE_PIN W18 IOSTANDARD LVCMOS33} [get_ports {QSPI_IO_0[2]}]
set_property -dict {PACKAGE_PIN W19 IOSTANDARD LVCMOS33} [get_ports {QSPI_IO_0[3]}]
#set_property -dict { PACKAGE_PIN U18 IOSTANDARD LVCMOS33 } [get_ports { ja[4] }]; #IO_L12P_T1_MRCC_34 Sch=ja_p[3]
## This file is a general .xdc for the PYNQ-Z2 board
## To use it in a project:
## - uncomment the lines corresponding to used pins
## - rename the used ports (in each line, after get_ports) according to the top level signal names in the project
## Clock signal 125 MHz
#set_property -dict { PACKAGE_PIN H16 IOSTANDARD LVCMOS33 } [get_ports { sysclk }]; #IO_L13P_T2_MRCC_35 Sch=sysclk
#create_clock -add -name sys_clk_pin -period 8.00 -waveform {0 4} [get_ports { sysclk }];
##Switches
#set_property -dict { PACKAGE_PIN M20 IOSTANDARD LVCMOS33 } [get_ports { sw[0] }]; #IO_L7N_T1_AD2N_35 Sch=sw[0]
#set_property -dict { PACKAGE_PIN M19 IOSTANDARD LVCMOS33 } [get_ports { sw[1] }]; #IO_L7P_T1_AD2P_35 Sch=sw[1]
##RGB LEDs
#set_property -dict { PACKAGE_PIN L15 IOSTANDARD LVCMOS33 } [get_ports { led4_b }]; #IO_L22N_T3_AD7N_35 Sch=led4_b
#set_property -dict { PACKAGE_PIN G17 IOSTANDARD LVCMOS33 } [get_ports { led4_g }]; #IO_L16P_T2_35 Sch=led4_g
#set_property -dict { PACKAGE_PIN N15 IOSTANDARD LVCMOS33 } [get_ports { led4_r }]; #IO_L21P_T3_DQS_AD14P_35 Sch=led4_r
#set_property -dict { PACKAGE_PIN G14 IOSTANDARD LVCMOS33 } [get_ports { led5_b }]; #IO_0_35 Sch=led5_b
#set_property -dict { PACKAGE_PIN L14 IOSTANDARD LVCMOS33 } [get_ports { led5_g }]; #IO_L22P_T3_AD7P_35 Sch=led5_g
#set_property -dict { PACKAGE_PIN M15 IOSTANDARD LVCMOS33 } [get_ports { led5_r }]; #IO_L23N_T3_35 Sch=led5_r
##LEDs
#set_property -dict { PACKAGE_PIN R14 IOSTANDARD LVCMOS33 } [get_ports { led[0] }]; #IO_L6N_T0_VREF_34 Sch=led[0]
#set_property -dict { PACKAGE_PIN P14 IOSTANDARD LVCMOS33 } [get_ports { led[1] }]; #IO_L6P_T0_34 Sch=led[1]
#set_property -dict { PACKAGE_PIN N16 IOSTANDARD LVCMOS33 } [get_ports { led[2] }]; #IO_L21N_T3_DQS_AD14N_35 Sch=led[2]
#set_property -dict { PACKAGE_PIN M14 IOSTANDARD LVCMOS33 } [get_ports { led[3] }]; #IO_L23P_T3_35 Sch=led[3]
##Buttons
#set_property -dict { PACKAGE_PIN D19 IOSTANDARD LVCMOS33 } [get_ports { btn[0] }]; #IO_L4P_T0_35 Sch=btn[0]
#set_property -dict { PACKAGE_PIN D20 IOSTANDARD LVCMOS33 } [get_ports { btn[1] }]; #IO_L4N_T0_35 Sch=btn[1]
#set_property -dict { PACKAGE_PIN L20 IOSTANDARD LVCMOS33 } [get_ports { btn[2] }]; #IO_L9N_T1_DQS_AD3N_35 Sch=btn[2]
#set_property -dict { PACKAGE_PIN L19 IOSTANDARD LVCMOS33 } [get_ports { btn[3] }]; #IO_L9P_T1_DQS_AD3P_35 Sch=btn[3]
##PmodA
##PmodB
#set_property -dict { PACKAGE_PIN W14 IOSTANDARD LVCMOS33 } [get_ports { jb[0] }]; #IO_L8P_T1_34 Sch=jb_p[1]
#set_property -dict { PACKAGE_PIN Y14 IOSTANDARD LVCMOS33 } [get_ports { jb[1] }]; #IO_L8N_T1_34 Sch=jb_n[1]
#set_property -dict { PACKAGE_PIN T11 IOSTANDARD LVCMOS33 } [get_ports { jb[2] }]; #IO_L1P_T0_34 Sch=jb_p[2]
#set_property -dict { PACKAGE_PIN T10 IOSTANDARD LVCMOS33 } [get_ports { jb[3] }]; #IO_L1N_T0_34 Sch=jb_n[2]
#set_property -dict { PACKAGE_PIN V16 IOSTANDARD LVCMOS33 } [get_ports { jb[4] }]; #IO_L18P_T2_34 Sch=jb_p[3]
#set_property -dict { PACKAGE_PIN W16 IOSTANDARD LVCMOS33 } [get_ports { jb[5] }]; #IO_L18N_T2_34 Sch=jb_n[3]
#set_property -dict { PACKAGE_PIN V12 IOSTANDARD LVCMOS33 } [get_ports { jb[6] }]; #IO_L4P_T0_34 Sch=jb_p[4]
#set_property -dict { PACKAGE_PIN W13 IOSTANDARD LVCMOS33 } [get_ports { jb[7] }]; #IO_L4N_T0_34 Sch=jb_n[4]
##Audio
#set_property -dict { PACKAGE_PIN M17 IOSTANDARD LVCMOS33 } [get_ports { adr0 }]; #IO_L8P_T1_AD10P_35 Sch=adr0
#set_property -dict { PACKAGE_PIN M18 IOSTANDARD LVCMOS33 } [get_ports { adr1 }]; #IO_L8N_T1_AD10N_35 Sch=adr1
#set_property -dict { PACKAGE_PIN U5 IOSTANDARD LVCMOS33 } [get_ports { au_mclk_r }]; #IO_L19N_T3_VREF_13 Sch=au_mclk_r
#set_property -dict { PACKAGE_PIN T9 IOSTANDARD LVCMOS33 } [get_ports { au_sda_r }]; #IO_L12P_T1_MRCC_13 Sch=au_sda_r
#set_property -dict { PACKAGE_PIN U9 IOSTANDARD LVCMOS33 } [get_ports { au_scl_r }]; #IO_L17P_T2_13 Sch= au_scl_r
#set_property -dict { PACKAGE_PIN F17 IOSTANDARD LVCMOS33 } [get_ports { au_dout_r }]; #IO_L6N_T0_VREF_35 Sch=au_dout_r
#set_property -dict { PACKAGE_PIN G18 IOSTANDARD LVCMOS33 } [get_ports { au_din_r }]; #IO_L16N_T2_35 Sch=au_din_r
#set_property -dict { PACKAGE_PIN T17 IOSTANDARD LVCMOS33 } [get_ports { au_wclk_r }]; #IO_L20P_T3_34 Sch=au_wclk_r
#set_property -dict { PACKAGE_PIN R18 IOSTANDARD LVCMOS33 } [get_ports { au_bclk_r }]; #IO_L20N_T3_34 Sch=au_bclk_r
## Single Ended Analog Inputs
##NOTE: The ar_an_p pins can be used as single ended analog inputs with voltages from 0-3.3V (Arduino Analog pins a[0]-a[5]).
## These signals should only be connected to the XADC core. When using these pins as digital I/O, use pins a[0]-a[5].
#set_property -dict { PACKAGE_PIN E17 IOSTANDARD LVCMOS33 } [get_ports { ar_an0_p }]; #IO_L3P_T0_DQS_AD1P_35 Sch=ar_an0_p
#set_property -dict { PACKAGE_PIN D18 IOSTANDARD LVCMOS33 } [get_ports { ar_an0_n }]; #IO_L3P_T0_DQS_AD1P_35 Sch=ar_an0_n
#set_property -dict { PACKAGE_PIN E18 IOSTANDARD LVCMOS33 } [get_ports { ar_an1_p }]; #IO_L5N_T0_AD9P_35 Sch=ar_an1_p
#set_property -dict { PACKAGE_PIN E19 IOSTANDARD LVCMOS33 } [get_ports { ar_an1_n }]; #IO_L5N_T0_AD9N_35 Sch=ar_an1_n
#set_property -dict { PACKAGE_PIN K14 IOSTANDARD LVCMOS33 } [get_ports { ar_an2_p }]; #IO_L20P_T3_AD6P_35 Sch=ar_an2_p
#set_property -dict { PACKAGE_PIN J14 IOSTANDARD LVCMOS33 } [get_ports { ar_an2_n }]; #IO_L20P_T3_AD6N_35 Sch=ar_an2_n
#set_property -dict { PACKAGE_PIN K16 IOSTANDARD LVCMOS33 } [get_ports { ar_an3_p }]; #IO_L24P_T3_AD15P_35 Sch=ar_an3_p
#set_property -dict { PACKAGE_PIN J16 IOSTANDARD LVCMOS33 } [get_ports { ar_an3_n }]; #IO_L24P_T3_AD15N_35 Sch=ar_an3_n
#set_property -dict { PACKAGE_PIN J20 IOSTANDARD LVCMOS33 } [get_ports { ar_an4_p }]; #IO_L17P_T2_AD5P_35 Sch=ar_an4_p
#set_property -dict { PACKAGE_PIN H20 IOSTANDARD LVCMOS33 } [get_ports { ar_an4_n }]; #IO_L17P_T2_AD5P_35 Sch=ar_an4_n
#set_property -dict { PACKAGE_PIN G19 IOSTANDARD LVCMOS33 } [get_ports { ar_an5_p }]; #IO_L18P_T2_AD13P_35 Sch=ar_an5_p
#set_property -dict { PACKAGE_PIN G20 IOSTANDARD LVCMOS33 } [get_ports { ar_an5_n }]; #IO_L18P_T2_AD13P_35 Sch=ar_an5_n
##Arduino Digital I/O
#set_property -dict { PACKAGE_PIN T14 IOSTANDARD LVCMOS33 } [get_ports { ar[0] }]; #IO_L5P_T0_34 Sch=ar[0]
#set_property -dict { PACKAGE_PIN U12 IOSTANDARD LVCMOS33 } [get_ports { ar[1] }]; #IO_L2N_T0_34 Sch=ar[1]
#set_property -dict { PACKAGE_PIN U13 IOSTANDARD LVCMOS33 } [get_ports { ar[2] }]; #IO_L3P_T0_DQS_PUDC_B_34 Sch=ar[2]
#set_property -dict { PACKAGE_PIN V13 IOSTANDARD LVCMOS33 } [get_ports { ar[3] }]; #IO_L3N_T0_DQS_34 Sch=ar[3]
#set_property -dict { PACKAGE_PIN V15 IOSTANDARD LVCMOS33 } [get_ports { ar[4] }]; #IO_L10P_T1_34 Sch=ar[4]
#set_property -dict { PACKAGE_PIN T15 IOSTANDARD LVCMOS33 } [get_ports { ar[5] }]; #IO_L5N_T0_34 Sch=ar[5]
#set_property -dict { PACKAGE_PIN R16 IOSTANDARD LVCMOS33 } [get_ports { ar[6] }]; #IO_L19P_T3_34 Sch=ar[6]
#set_property -dict { PACKAGE_PIN U17 IOSTANDARD LVCMOS33 } [get_ports { ar[7] }]; #IO_L9N_T1_DQS_34 Sch=ar[7]
#set_property -dict { PACKAGE_PIN V17 IOSTANDARD LVCMOS33 } [get_ports { ar[8] }]; #IO_L21P_T3_DQS_34 Sch=ar[8]
#set_property -dict { PACKAGE_PIN V18 IOSTANDARD LVCMOS33 } [get_ports { ar[9] }]; #IO_L21N_T3_DQS_34 Sch=ar[9]
#set_property -dict { PACKAGE_PIN T16 IOSTANDARD LVCMOS33 } [get_ports { ar[10] }]; #IO_L9P_T1_DQS_34 Sch=ar[10]
#set_property -dict { PACKAGE_PIN R17 IOSTANDARD LVCMOS33 } [get_ports { ar[11] }]; #IO_L19N_T3_VREF_34 Sch=ar[11]
#set_property -dict { PACKAGE_PIN P18 IOSTANDARD LVCMOS33 } [get_ports { ar[12] }]; #IO_L23N_T3_34 Sch=ar[12]
#set_property -dict { PACKAGE_PIN N17 IOSTANDARD LVCMOS33 } [get_ports { ar[13] }]; #IO_L23P_T3_34 Sch=ar[13]
#set_property -dict { PACKAGE_PIN Y13 IOSTANDARD LVCMOS33 } [get_ports { a }]; #IO_L20N_T3_13 Sch=a
##Arduino Digital I/O On Outer Analog Header
##NOTE: These pins should be used when using the analog header signals A0-A5 as digital I/O
#set_property -dict { PACKAGE_PIN Y11 IOSTANDARD LVCMOS33 } [get_ports { a[0] }]; #IO_L18N_T2_13 Sch=a[0]
#set_property -dict { PACKAGE_PIN Y12 IOSTANDARD LVCMOS33 } [get_ports { a[1] }]; #IO_L20P_T3_13 Sch=a[1]
#set_property -dict { PACKAGE_PIN W11 IOSTANDARD LVCMOS33 } [get_ports { a[2] }]; #IO_L18P_T2_13 Sch=a[2]
#set_property -dict { PACKAGE_PIN V11 IOSTANDARD LVCMOS33 } [get_ports { a[3] }]; #IO_L21P_T3_DQS_13 Sch=a[3]
#set_property -dict { PACKAGE_PIN T5 IOSTANDARD LVCMOS33 } [get_ports { a[4] }]; #IO_L19P_T3_13 Sch=a[4]
#set_property -dict { PACKAGE_PIN U10 IOSTANDARD LVCMOS33 } [get_ports { a[5] }]; #IO_L12N_T1_MRCC_13 Sch=a[5]
## Arduino SPI
#set_property -dict { PACKAGE_PIN W15 IOSTANDARD LVCMOS33 } [get_ports { ck_miso }]; #IO_L10N_T1_34 Sch=miso
#set_property -dict { PACKAGE_PIN T12 IOSTANDARD LVCMOS33 } [get_ports { ck_mosi }]; #IO_L2P_T0_34 Sch=ar_mosi_r
#set_property -dict { PACKAGE_PIN H15 IOSTANDARD LVCMOS33 } [get_ports { ck_sck }]; #IO_L19P_T3_35 Sch=sck
#set_property -dict { PACKAGE_PIN F16 IOSTANDARD LVCMOS33 } [get_ports { ck_ss }]; #IO_L6P_T0_35 Sch=ss
## Arduino I2C
#set_property -dict { PACKAGE_PIN P16 IOSTANDARD LVCMOS33 } [get_ports { ar_scl }]; #IO_L24N_T3_34 Sch=ar_scl
#set_property -dict { PACKAGE_PIN P15 IOSTANDARD LVCMOS33 } [get_ports { ar_sda }]; #IO_L24P_T3_34 Sch=ar_sda
##Raspberry Digital I/O
#set_property -dict { PACKAGE_PIN W18 IOSTANDARD LVCMOS33 } [get_ports { rpio_02_r }]; #IO_L22P_T3_34 Sch=rpio_02_r
#set_property -dict { PACKAGE_PIN W19 IOSTANDARD LVCMOS33 } [get_ports { rpio_03_r }]; #IO_L22N_T3_34 Sch=rpio_03_r
#set_property -dict { PACKAGE_PIN Y18 IOSTANDARD LVCMOS33 } [get_ports { rpio_04_r }]; #IO_L17P_T2_34 Sch=rpio_04_r
#set_property -dict { PACKAGE_PIN Y19 IOSTANDARD LVCMOS33 } [get_ports { rpio_05_r }]; #IO_L17N_T2_34 Sch=rpio_05_r
#set_property -dict { PACKAGE_PIN U18 IOSTANDARD LVCMOS33 } [get_ports { rpio_06_r }]; #IO_L22P_T3_13 Sch=rpio_06_r
#set_property -dict { PACKAGE_PIN U19 IOSTANDARD LVCMOS33 } [get_ports { rpio_07_r }]; #IO_L12P_T1_MRCC_34 Sch=rpio_07_r
#set_property -dict { PACKAGE_PIN F19 IOSTANDARD LVCMOS33 } [get_ports { rpio_08_r }]; #IO_L12N_T1_MRCC_34 Sch=rpio_08_r
#set_property -dict { PACKAGE_PIN V10 IOSTANDARD LVCMOS33 } [get_ports { rpio_09_r }]; #IO_L21N_T3_DQS_13 Sch=rpio_09_r
#set_property -dict { PACKAGE_PIN V8 IOSTANDARD LVCMOS33 } [get_ports { rpio_10_r }]; #IO_L15P_T2_DQS_13 Sch=rpio_10_r
#set_property -dict { PACKAGE_PIN W10 IOSTANDARD LVCMOS33 } [get_ports { rpio_11_r }]; #IO_L16P_T2_13 Sch=rpio_11_r
#set_property -dict { PACKAGE_PIN B20 IOSTANDARD LVCMOS33 } [get_ports { rpio_12_r }]; #IO_L1N_T0_AD0N_35 Sch=rpio_12_r
#set_property -dict { PACKAGE_PIN W8 IOSTANDARD LVCMOS33 } [get_ports { rpio_13_r }]; #IO_L15N_T2_DQS_13 Sch=rpio_13_r
#set_property -dict { PACKAGE_PIN V6 IOSTANDARD LVCMOS33 } [get_ports { rpio_14_r }]; #IO_L22P_T3_13 Sch=rpio_14_r
#set_property -dict { PACKAGE_PIN Y6 IOSTANDARD LVCMOS33 } [get_ports { rpio_15_r }]; #IO_L13N_T2_MRCC_13 Sch=rpio_15_r
#set_property -dict { PACKAGE_PIN B19 IOSTANDARD LVCMOS33 } [get_ports { rpio_16_r }]; #IO_L2P_T0_AD8P_35 Sch=rpio_16_r
#set_property -dict { PACKAGE_PIN U7 IOSTANDARD LVCMOS33 } [get_ports { rpio_17_r }]; #IO_L11P_T1_SRCC_13 Sch=rpio_17_r
#set_property -dict { PACKAGE_PIN C20 IOSTANDARD LVCMOS33 } [get_ports { rpio_18_r }]; #IO_L1P_T0_AD0P_35 Sch=rpio_18_r
#set_property -dict { PACKAGE_PIN Y8 IOSTANDARD LVCMOS33 } [get_ports { rpio_19_r }]; #IO_L14N_T2_SRCC_13 Sch=rpio_19_r
#set_property -dict { PACKAGE_PIN A20 IOSTANDARD LVCMOS33 } [get_ports { rpio_20_r }]; #IO_L2N_T0_AD8N_35 Sch=rpio_20_r
#set_property -dict { PACKAGE_PIN Y9 IOSTANDARD LVCMOS33 } [get_ports { rpio_21_r }]; #IO_L14P_T2_SRCC_13 Sch=rpio_21_r
#set_property -dict { PACKAGE_PIN U8 IOSTANDARD LVCMOS33 } [get_ports { rpio_22_r }]; #IO_L17N_T2_13 Sch=rpio_22_r
#set_property -dict { PACKAGE_PIN W6 IOSTANDARD LVCMOS33 } [get_ports { rpio_23_r }]; #IO_IO_L22N_T3_13 Sch=rpio_23_r
#set_property -dict { PACKAGE_PIN Y7 IOSTANDARD LVCMOS33 } [get_ports { rpio_24_r }]; #IO_L13P_T2_MRCC_13 Sch=rpio_24_r
#set_property -dict { PACKAGE_PIN F20 IOSTANDARD LVCMOS33 } [get_ports { rpio_25_r }]; #IO_L15N_T2_DQS_AD12N_35 Sch=rpio_25_r
#set_property -dict { PACKAGE_PIN W9 IOSTANDARD LVCMOS33 } [get_ports { rpio_26_r }]; #IO_L16N_T2_13 Sch=rpio_26_r
#set_property -dict { PACKAGE_PIN Y16 IOSTANDARD LVCMOS33 } [get_ports { rpio_sd_r }]; #IO_L7P_T1_34 Sch=rpio_sd_r
#set_property -dict { PACKAGE_PIN Y17 IOSTANDARD LVCMOS33 } [get_ports { rpio_sc_r }]; #IO_L7N_T1_34 Sch=rpio_sc_r
##HDMI Rx
#set_property -dict { PACKAGE_PIN H17 IOSTANDARD LVCMOS33 } [get_ports { hdmi_rx_cec }]; #IO_L13N_T2_MRCC_35 Sch=hdmi_rx_cec
#set_property -dict { PACKAGE_PIN P19 IOSTANDARD TMDS_33 } [get_ports { hdmi_rx_clk_n }]; #IO_L13N_T2_MRCC_34 Sch=hdmi_rx_clk_n
#set_property -dict { PACKAGE_PIN N18 IOSTANDARD TMDS_33 } [get_ports { hdmi_rx_clk_p }]; #IO_L13P_T2_MRCC_34 Sch=hdmi_rx_clk_p
#set_property -dict { PACKAGE_PIN W20 IOSTANDARD TMDS_33 } [get_ports { hdmi_rx_d_n[0] }]; #IO_L16N_T2_34 Sch=hdmi_rx_d_n[0]
#set_property -dict { PACKAGE_PIN V20 IOSTANDARD TMDS_33 } [get_ports { hdmi_rx_d_p[0] }]; #IO_L16P_T2_34 Sch=hdmi_rx_d_p[0]
#set_property -dict { PACKAGE_PIN U20 IOSTANDARD TMDS_33 } [get_ports { hdmi_rx_d_n[1] }]; #IO_L15N_T2_DQS_34 Sch=hdmi_rx_d_n[1]
#set_property -dict { PACKAGE_PIN T20 IOSTANDARD TMDS_33 } [get_ports { hdmi_rx_d_p[1] }]; #IO_L15P_T2_DQS_34 Sch=hdmi_rx_d_p[1]
#set_property -dict { PACKAGE_PIN P20 IOSTANDARD TMDS_33 } [get_ports { hdmi_rx_d_n[2] }]; #IO_L14N_T2_SRCC_34 Sch=hdmi_rx_d_n[2]
#set_property -dict { PACKAGE_PIN N20 IOSTANDARD TMDS_33 } [get_ports { hdmi_rx_d_p[2] }]; #IO_L14P_T2_SRCC_34 Sch=hdmi_rx_d_p[2]
#set_property -dict { PACKAGE_PIN T19 IOSTANDARD LVCMOS33 } [get_ports { hdmi_rx_hpd }]; #IO_25_34 Sch=hdmi_rx_hpd
#set_property -dict { PACKAGE_PIN U14 IOSTANDARD LVCMOS33 } [get_ports { hdmi_rx_scl }]; #IO_L11P_T1_SRCC_34 Sch=hdmi_rx_scl
#set_property -dict { PACKAGE_PIN U15 IOSTANDARD LVCMOS33 } [get_ports { hdmi_rx_sda }]; #IO_L11N_T1_SRCC_34 Sch=hdmi_rx_sda
##HDMI Tx
#set_property -dict { PACKAGE_PIN G15 IOSTANDARD LVCMOS33 } [get_ports { hdmi_tx_cec }]; #IO_L19N_T3_VREF_35 Sch=hdmi_tx_cec
#set_property -dict { PACKAGE_PIN L17 IOSTANDARD TMDS_33 } [get_ports { hdmi_tx_clk_n }]; #IO_L11N_T1_SRCC_35 Sch=hdmi_tx_clk_n
#set_property -dict { PACKAGE_PIN L16 IOSTANDARD TMDS_33 } [get_ports { hdmi_tx_clk_p }]; #IO_L11P_T1_SRCC_35 Sch=hdmi_tx_clk_p
#set_property -dict { PACKAGE_PIN K18 IOSTANDARD TMDS_33 } [get_ports { hdmi_tx_d_n[0] }]; #IO_L12N_T1_MRCC_35 Sch=hdmi_tx_d_n[0]
#set_property -dict { PACKAGE_PIN K17 IOSTANDARD TMDS_33 } [get_ports { hdmi_tx_d_p[0] }]; #IO_L12P_T1_MRCC_35 Sch=hdmi_tx_d_p[0]
#set_property -dict { PACKAGE_PIN J19 IOSTANDARD TMDS_33 } [get_ports { hdmi_tx_d_n[1] }]; #IO_L10N_T1_AD11N_35 Sch=hdmi_tx_d_n[1]
#set_property -dict { PACKAGE_PIN K19 IOSTANDARD TMDS_33 } [get_ports { hdmi_tx_d_p[1] }]; #IO_L10P_T1_AD11P_35 Sch=hdmi_tx_d_p[1]
#set_property -dict { PACKAGE_PIN H18 IOSTANDARD TMDS_33 } [get_ports { hdmi_tx_d_n[2] }]; #IO_L14N_T2_AD4N_SRCC_35 Sch=hdmi_tx_d_n[2]
#set_property -dict { PACKAGE_PIN J18 IOSTANDARD TMDS_33 } [get_ports { hdmi_tx_d_p[2] }]; #IO_L14P_T2_AD4P_SRCC_35 Sch=hdmi_tx_d_p[2]
#set_property -dict { PACKAGE_PIN R19 IOSTANDARD LVCMOS33 } [get_ports { hdmi_tx_hpdn }]; #IO_0_34 Sch=hdmi_tx_hpdn
##Crypto SDA
#set_property -dict { PACKAGE_PIN J15 IOSTANDARD LVCMOS33 } [get_ports { crypto_sda }]; #IO_25_35 Sch=crypto_sda
set_input_delay -clock [get_clocks clk_fpga_0] -min -add_delay 2.000 [get_ports {QSPI_IO_0[*]}]
set_input_delay -clock [get_clocks clk_fpga_0] -max -add_delay 5.000 [get_ports {QSPI_IO_0[*]}]
create_generated_clock -name ahb_qspi_i/AXI_QSPI_0/inst/ahb_qspi_fpga_wrapper_0/inst/u_top_ahb_qspi/u_ahb_qspi_interface/AHB_QSPI_ENABLE -source [get_pins {ahb_qspi_i/processing_system7_0/inst/PS7_i/FCLKCLK[0]}] -divide_by 1 [get_pins ahb_qspi_i/AXI_QSPI_0/inst/ahb_qspi_fpga_wrapper_0/inst/u_top_ahb_qspi/u_ahb_qspi_interface/AHB_QSPI_ENABLE_reg/Q]
create_generated_clock -name ahb_qspi_i/AXI_QSPI_0/inst/ahb_qspi_fpga_wrapper_0/inst/u_top_ahb_qspi/u_apb_qspi_regs/APB_QSPI_ENABLE -source [get_pins {ahb_qspi_i/processing_system7_0/inst/PS7_i/FCLKCLK[0]}] -divide_by 1 [get_pins {ahb_qspi_i/AXI_QSPI_0/inst/ahb_qspi_fpga_wrapper_0/inst/u_top_ahb_qspi/u_apb_qspi_regs/reg2_reg[8]/Q}]
create_generated_clock -name ahb_qspi_i/AXI_QSPI_0/inst/ahb_qspi_fpga_wrapper_0/inst/u_top_ahb_qspi/u_qspi_controller/QSPI_SCLK_e -source [get_pins {ahb_qspi_i/processing_system7_0/inst/PS7_i/FCLKCLK[0]}] -divide_by 1 [get_pins ahb_qspi_i/AXI_QSPI_0/inst/ahb_qspi_fpga_wrapper_0/inst/u_top_ahb_qspi/u_qspi_controller/QSPI_SCLK_e_reg/Q]
set_clock_groups -logically_exclusive -group [get_clocks -include_generated_clocks ahb_qspi_i/AXI_QSPI_0/inst/ahb_qspi_fpga_wrapper_0/inst/u_top_ahb_qspi/u_apb_qspi_regs/APB_QSPI_ENABLE] -group [get_clocks -include_generated_clocks ahb_qspi_i/AXI_QSPI_0/inst/ahb_qspi_fpga_wrapper_0/inst/u_top_ahb_qspi/u_ahb_qspi_interface/AHB_QSPI_ENABLE]
set_property C_CLK_INPUT_FREQ_HZ 300000000 [get_debug_cores dbg_hub]
set_property C_ENABLE_CLK_DIVIDER false [get_debug_cores dbg_hub]
set_property C_USER_SCAN_CHAIN 1 [get_debug_cores dbg_hub]
connect_debug_port dbg_hub/clk [get_nets clk]
fpga/pynq_z2/ahb_qspi_fpga_wrapper.v 0 → 100644
+ 101
− 0
View file @ f9f935b5
module ahb_qspi_fpga_wrapper (
(* X_INTERFACE_INFO = "xilinx.com:signal:clock:1.0 CLK.HCLK CLK" *) (* X_INTERFACE_PARAMETER = "XIL_INTERFACENAME CLK.HCLK, ASSOCIATED_RESET HRESETn, CLK_DOMAIN ahb_qspi_ip_HCLK, FREQ_HZ 10000000, FREQ_TOLERANCE_HZ 0, INSERT_VIP 0, PHASE 0.0" *) input HCLK,
(* X_INTERFACE_INFO = "xilinx.com:signal:reset:1.0 RST.HRESETN RST" *) (* X_INTERFACE_PARAMETER = "XIL_INTERFACENAME RST.HRESETN, INSERT_VIP 0, POLARITY ACTIVE_LOW" *) input HRESETn,
(* X_INTERFACE_INFO = "xilinx.com:signal:clock:1.0 CLK.PCLK CLK" *) (* X_INTERFACE_PARAMETER = "XIL_INTERFACENAME CLK.PCLK, ASSOCIATED_RESET PRESETn, CLK_DOMAIN ahb_qspi_ip_PCLK, FREQ_HZ 10000000, FREQ_TOLERANCE_HZ 0, INSERT_VIP 0, PHASE 0.0" *) input PCLK,
(* X_INTERFACE_INFO = "xilinx.com:signal:reset:1.0 RST.PRESETN RST" *) (* X_INTERFACE_PARAMETER = "XIL_INTERFACENAME RST.PRESETN, INSERT_VIP 0, POLARITY ACTIVE_LOW" *) input PRESETn,
(* X_INTERFACE_INFO = "xilinx.com:interface:ahblite:2.0 S_AHB SEL" *)
input S_AHB_HSEL, // Slave select (required) S_AHB
(* X_INTERFACE_INFO = "xilinx.com:interface:ahblite:2.0 S_AHB HADDR" *)
input [31:0] S_AHB_HADDR, // Address bus (required) S_AHB
(* X_INTERFACE_INFO = "xilinx.com:interface:ahblite:2.0 S_AHB HPROT" *)
input [3:0] S_AHB_HPROT, // Protection type (required) S_AHB
(* X_INTERFACE_INFO = "xilinx.com:interface:ahblite:2.0 S_AHB HTRANS" *)
input [1:0] S_AHB_HTRANS, // Transfer type (required) S_AHB
(* X_INTERFACE_INFO = "xilinx.com:interface:ahblite:2.0 S_AHB HSIZE" *)
input [2:0] S_AHB_HSIZE, // Transfer size (required) S_AHB
(* X_INTERFACE_INFO = "xilinx.com:interface:ahblite:2.0 S_AHB HWRITE" *)
input S_AHB_HWRITE, // Write / Read transfer (required) S_AHB
(* X_INTERFACE_INFO = "xilinx.com:interface:ahblite:2.0 S_AHB HBURST" *)
input [2:0] S_AHB_HBURST, // Burst type (required) S_AHB
(* X_INTERFACE_INFO = "xilinx.com:interface:ahblite:2.0 S_AHB HWDATA" *)
input [31:0] S_AHB_HWDATA, // Write data (required) S_AHB
(* X_INTERFACE_INFO = "xilinx.com:interface:ahblite:2.0 S_AHB HRDATA" *)
output [31:0] S_AHB_HRDATA, // Read data (required) S_AHB
(* X_INTERFACE_INFO = "xilinx.com:interface:ahblite:2.0 S_AHB HRESP" *)
output S_AHB_HRESP, // Status of the transfer (required) S_AHB
(* X_INTERFACE_INFO = "xilinx.com:interface:ahblite:2.0 S_AHB HREADY_IN" *)
input S_AHB_HREADY_IN, // This signal indicates that the previous transfer is complete. (required)
(* X_INTERFACE_INFO = "xilinx.com:interface:ahblite:2.0 S_AHB HREADY_OUT" *)
output S_AHB_HREADY_OUT, // This signal indicates that the transfer is complete. (required)
// additional ports here
(* X_INTERFACE_INFO = "xilinx.com:interface:apb:1.0 apb_interface PADDR" *)
input [31:0] apb_interface_PADDR, // Address (required) apb
(* X_INTERFACE_INFO = "xilinx.com:interface:apb:1.0 apb_interface PPROT" *)
input [2:0] apb_interface_PPROT, // Protection (optional) apb
(* X_INTERFACE_INFO = "xilinx.com:interface:apb:1.0 apb_interface PSEL" *)
input apb_interface_PSEL, // Slave Select (required) apb
(* X_INTERFACE_INFO = "xilinx.com:interface:apb:1.0 apb_interface PENABLE" *)
input apb_interface_PENABLE, // Enable (required) apb
(* X_INTERFACE_INFO = "xilinx.com:interface:apb:1.0 apb_interface PWRITE" *)
input apb_interface_PWRITE, // Write Control (required) apb
(* X_INTERFACE_INFO = "xilinx.com:interface:apb:1.0 apb_interface PWDATA" *)
input [31:0] apb_interface_PWDATA, // Write Data (required) apb
(* X_INTERFACE_INFO = "xilinx.com:interface:apb:1.0 apb_interface PSTRB" *)
input [3:0] apb_interface_PSTRB, // Write data strobe (optionaapb_
(* X_INTERFACE_INFO = "xilinx.com:interface:apb:1.0 apb_interface PREADY" *)
output apb_interface_PREADY, // Slave Ready (required) apb
(* X_INTERFACE_INFO = "xilinx.com:interface:apb:1.0 apb_interface PRDATA" *)
output [31:0] apb_interface_PRDATA, // Read Data (required) apb
(* X_INTERFACE_INFO = "xilinx.com:interface:apb:1.0 apb_interface PSLVERR" *)
output apb_interface_PSLVERR, // Slave Error Response (required)
output wire [3:0] QSPI_IO_o,
input wire [3:0] QSPI_IO_i,
output wire [3:0] QSPI_IO_e,
output wire QSPI_SCLK,
output wire QSPI_nCS
);
top_ahb_qspi u_top_ahb_qspi(
.HCLK (HCLK),
.HRESETn (HRESETn),
.PCLK (PCLK),
.PRESETn (PRESETn),
.HADDR (S_AHB_HADDR),
.HTRANS (S_AHB_HTRANS),
.HWRITE (S_AHB_HWRITE),
.HSIZE (S_AHB_HSIZE),
.HBURST (S_AHB_HBURST),
.HPROT (S_AHB_HPROT),
.HWDATA (S_AHB_HWDATA),
.HSELx (1'b1),
.HRDATA (S_AHB_HRDATA),
.HREADY (1'b1),
.HREADYOUT (S_AHB_HREADY_OUT),
.HRESP (S_AHB_HRESP),
.PADDR (apb_interface_PADDR[15:0]),
.PPROT (apb_interface_PPROT),
.PSEL (apb_interface_PSEL),
.PENABLE (apb_interface_PENABLE),
.PWRITE (apb_interface_PWRITE),
.PWDATA (apb_interface_PWDATA),
.PSTRB (apb_interface_PSTRB),
.PRDATA (apb_interface_PRDATA),
.PREADY (apb_interface_PREADY),
.PSLVERR (apb_interface_PSLVERR),
.QSPI_SCLK (QSPI_SCLK),
.QSPI_nCS (QSPI_nCS),
.QSPI_IO_o (QSPI_IO_o),
.QSPI_IO_i (QSPI_IO_i),
.QSPI_IO_e (QSPI_IO_e)
);
endmodule
\ No newline at end of file
logical/ahb_qspi_interface/logical/ahb_qspi_interface.sv
+ 2
− 18
View file @ f9f935b5
......@@ -26,7 +26,7 @@ module ahb_qspi_interface #(
output wire AHB_QSPI_WRITE,
output wire AHB_QSPI_ADDR_EN,
output wire [3:0] AHB_QSPI_DUMMY_CYCLES,
output reg [3:0] AHB_QSPI_N_RW_BYTES,
output wire [3:0] AHB_QSPI_N_RW_BYTES,
output reg [21:0] AHB_QSPI_ADDR,
output wire [127:0] AHB_QSPI_WDATA,
......@@ -44,6 +44,7 @@ assign AHB_QSPI_DUMMY_CYCLES = 4'h4;
assign AHB_QSPI_READ=1'b1;
assign AHB_QSPI_WRITE=1'b0;
assign AHB_QSPI_WDATA = HWDATA;
assign AHB_QSPI_N_RW_BYTES = 4'hF;
wire [31:0] AHB_QSPI_RDATA_W0 = {AHB_QSPI_RDATA[71:64],AHB_QSPI_RDATA[79:72],AHB_QSPI_RDATA[87:80],AHB_QSPI_RDATA[95:88]}; //AHB_QSPI_RDATA[95:64];
......@@ -96,26 +97,9 @@ always @(*) begin
IDLE: if(HTRANS==2'b00)
next_state = IDLE;
else if(HSELx & HWRITE & ~qspi_ready) begin
case(HSIZE)
3'b000: AHB_QSPI_N_RW_BYTES = 4'hF;
3'b001: AHB_QSPI_N_RW_BYTES = 4'hF;
3'b010: AHB_QSPI_N_RW_BYTES = 4'hF;
3'b011: AHB_QSPI_N_RW_BYTES = 4'hF;
3'b100: AHB_QSPI_N_RW_BYTES = 4'hF;
default: AHB_QSPI_N_RW_BYTES = 4'hF;
endcase
next_state = WAIT_WRITE;
end
else if(HSELx & ~qspi_ready) begin
case(HSIZE)
3'b000: AHB_QSPI_N_RW_BYTES = 4'hF;
3'b001: AHB_QSPI_N_RW_BYTES = 4'hF;
3'b010: AHB_QSPI_N_RW_BYTES = 4'hF;
3'b011: AHB_QSPI_N_RW_BYTES = 4'hF;
3'b100: AHB_QSPI_N_RW_BYTES = 4'hF;
default: AHB_QSPI_N_RW_BYTES = 4'hF;
endcase
next_state = WAIT_READ;
end
WAIT_WRITE: if(qspi_ready)
......
logical/apb_qspi_regs/logical/apb_qspi_regs.v
+ 1
− 0
View file @ f9f935b5
......@@ -132,6 +132,7 @@ always @(PCLK, PADDR) begin
10'h009: PRDATA = reg9;
10'h00A: PRDATA = reg10;
10'h00B: PRDATA = reg11;
default: PRDATA = 32'hDEADCAFE;
endcase
end
end
......
logical/qspi_controller/logical/qspi_controller.sv
+ 22
− 38
View file @ f9f935b5
......@@ -326,45 +326,29 @@ always @(posedge QSPI_SCLK_i) begin
end
// RDATA latch
always @(posedge QSPI_nCS or negedge HRESETn) begin
if(~HRESETn)
QSPI_RDATA <= 128'd0;
else begin
if(QSPI_N_RW_BYTES==4'h0)
QSPI_RDATA <= {{120{1'b0}}, data_in_reg[7:0 ]};
else if(QSPI_N_RW_BYTES==4'h1)
QSPI_RDATA <= {{112{1'b0}}, data_in_reg[15:0]};
else if(QSPI_N_RW_BYTES==4'h2)
QSPI_RDATA <= {{104{1'b0}}, data_in_reg[23:0]};
else if(QSPI_N_RW_BYTES==4'h3)
QSPI_RDATA <= {{96{1'b0}}, data_in_reg[31:0]};
else if(QSPI_N_RW_BYTES==4'h4)
QSPI_RDATA <= {{88{1'b0}}, data_in_reg[31:0], data_in_reg[39:32]};
else if(QSPI_N_RW_BYTES==4'h5)
QSPI_RDATA <= {{80{1'b0}}, data_in_reg[31:0], data_in_reg[47:32]};
else if(QSPI_N_RW_BYTES==4'h6)
QSPI_RDATA <= {{72{1'b0}}, data_in_reg[31:0], data_in_reg[55:32]};
else if(QSPI_N_RW_BYTES==4'h7)
QSPI_RDATA <= {{64{1'b0}}, data_in_reg[31:0], data_in_reg[63:32]};
else if(QSPI_N_RW_BYTES==4'h8)
QSPI_RDATA <= {{56{1'b0}}, data_in_reg[31:0], data_in_reg[63:32], data_in_reg[71:64]};
else if(QSPI_N_RW_BYTES==4'h9)
QSPI_RDATA <= {{48{1'b0}}, data_in_reg[31:0], data_in_reg[63:32], data_in_reg[79:64]};
else if(QSPI_N_RW_BYTES==4'hA)
QSPI_RDATA <= {{40{1'b0}}, data_in_reg[31:0], data_in_reg[63:32], data_in_reg[87:64]};
else if(QSPI_N_RW_BYTES==4'hB)
QSPI_RDATA <= {{32{1'b0}}, data_in_reg[31:0], data_in_reg[63:32], data_in_reg[95:64]};
else if(QSPI_N_RW_BYTES==4'hC)
QSPI_RDATA <= {{24{1'b0}}, data_in_reg[31:0], data_in_reg[63:32], data_in_reg[95:64], data_in_reg[103:96]};
else if(QSPI_N_RW_BYTES==4'hD)
QSPI_RDATA <= {{16{1'b0}}, data_in_reg[31:0], data_in_reg[63:32], data_in_reg[95:64], data_in_reg[111:96]};
else if(QSPI_N_RW_BYTES==4'hE)
QSPI_RDATA <= {{8{1'b0}}, data_in_reg[31:0], data_in_reg[63:32], data_in_reg[95:64], data_in_reg[119:96]};
else if(QSPI_N_RW_BYTES==4'hF)
QSPI_RDATA <= {data_in_reg[31:0], data_in_reg[63:32], data_in_reg[95:64], data_in_reg[127:96]};
always @(*) begin
if(~HRESETn) begin
QSPI_RDATA = 128'd0;
end else if(QSPI_nCS) begin
case(QSPI_N_RW_BYTES)
4'h0: QSPI_RDATA = {{120{1'b0}}, data_in_reg[7:0 ]};
4'h1: QSPI_RDATA = {{112{1'b0}}, data_in_reg[15:0]};
4'h2: QSPI_RDATA = {{104{1'b0}}, data_in_reg[23:0]};
4'h3: QSPI_RDATA = {{96{1'b0}}, data_in_reg[31:0]};
4'h4: QSPI_RDATA = {{88{1'b0}}, data_in_reg[31:0], data_in_reg[39:32]};
4'h5: QSPI_RDATA = {{80{1'b0}}, data_in_reg[31:0], data_in_reg[47:32]};
4'h6: QSPI_RDATA = {{72{1'b0}}, data_in_reg[31:0], data_in_reg[55:32]};
4'h7: QSPI_RDATA = {{64{1'b0}}, data_in_reg[31:0], data_in_reg[63:32]};
4'h8: QSPI_RDATA = {{56{1'b0}}, data_in_reg[31:0], data_in_reg[63:32], data_in_reg[71:64]};
4'h9: QSPI_RDATA = {{48{1'b0}}, data_in_reg[31:0], data_in_reg[63:32], data_in_reg[79:64]};
4'hA: QSPI_RDATA = {{40{1'b0}}, data_in_reg[31:0], data_in_reg[63:32], data_in_reg[87:64]};
4'hB: QSPI_RDATA = {{32{1'b0}}, data_in_reg[31:0], data_in_reg[63:32], data_in_reg[95:64]};
4'hC: QSPI_RDATA = {{24{1'b0}}, data_in_reg[31:0], data_in_reg[63:32], data_in_reg[95:64], data_in_reg[103:96]};
4'hD: QSPI_RDATA = {{16{1'b0}}, data_in_reg[31:0], data_in_reg[63:32], data_in_reg[95:64], data_in_reg[111:96]};
4'hE: QSPI_RDATA = {{8{1'b0}}, data_in_reg[31:0], data_in_reg[63:32], data_in_reg[95:64], data_in_reg[119:96]};
4'hF: QSPI_RDATA = {data_in_reg[31:0], data_in_reg[63:32], data_in_reg[95:64], data_in_reg[127:96]};
endcase
end
end
assign QSPI_nCS = ((QSPI_ENABLE==1'b1) ||(current_state!=IDLE) || (QSPI_SCLK_e==1'b1))?1'b0:1'b1;
......
0% or .
You are about to add 0 people to the discussion. Proceed with caution.
Please register or to comment