Add IRQ and gate level sims

.gitignore

@@ -24,6 +24,14 @@ asic/TSMC28nm/default.svf
 asic/TSMC28nm/*.log
 asic/TSMC28nm/alib-52
 
+asic/TSMC65nm/*.mr
+asic/TSMC65nm/*pvl
+asic/TSMC65nm/*.syn
+asic/TSMC65nm/command.log
+asic/TSMC65nm/default.svf
+asic/TSMC65nm/*.log
+asic/TSMC65nm/alib-52
+
 docs/tex/*.aux
 docs/tex/*.log
 docs/tex/*.out

README.md

@@ -23,6 +23,9 @@ The APB is mapped between the QSPI controller and Flash Cache configuration regi
 - 0x0000-0x0FFF : QSPI controller
 - 0x1000-0x1FFF : Flash Cache
 
+## Interrupts
+Only 1 interrupt currently for when QSPI has finished a transfer. To clear interrupt write a 1 to 8th bit of status register.
+
 ## Simulation
 The AHB QSPI includes a cocoTB simulation environment. This can be run using the `make run_cocotb` command
 
@@ -37,7 +40,6 @@ Read bandwidth with 4 KB cache for 512x 32 bit reads, and system clock of 200 MH
 - Add programmable clock divider for QSPI
 - Add programmable op codes for AHB interface
 - Improve writing method over APB? (see below)
-- Add interrupts for QSPI finish
 - Add programmable address length (currently this is set to the maximum of the CG092 flash cache. If we want to increase this then we need a new cache)
 
 ## Writing over APB

asic/TSMC28nm/dc_synthesis.tcl

@@ -18,5 +18,3 @@ compile_ultra
 
 write -format verilog -hierarchy -output $env(SOCLABS_AHB_QSPI_DIR)/imp/ASIC/top_ahb_qspi_gates.v
 write_sdf -version 2.1 $env(SOCLABS_AHB_QSPI_DIR)/imp/ASIC/top_ahb_qspi.sdf
-
-exit
\ No newline at end of file

asic/TSMC65nm/ahb_qspi_constraints.sdc

+
+set HCLK "HCLK"
+set PCLK "PCLK"
+
+set HCLK_PERIOD 10
+set PCLK_PERIOD 10
+
+create_clock -name "$HCLK" -period $HCLK_PERIOD [get_ports HCLK]
+create_clock -name "$PCLK" -period $PCLK_PERIOD [get_ports PCLK]
+create_generated_clock -name "QSPI_SCLK" -source [get_ports HCLK] -divide_by 2 [get_pins u_top_ahb_qspi/u_qspi_controller/u_qspi_clock_div/QSPI_SCLK_i]
+create_generated_clock -name "QSPI_SCLK_o" -source [get_pins u_top_ahb_qspi/u_qspi_controller/u_qspi_clock_div/QSPI_SCLK_i] -divide_by 1 [get_ports QSPI_SCLK]
+
+
+set_max_fanout 10 [all_inputs]
+
+set_input_delay  1 -clock "QSPI_SCLK_o" [get_ports QSPI_IO[*]]
+set_output_delay 1 -clock "QSPI_SCLK_o" [get_ports QSPI_IO[*]]

asic/TSMC65nm/dc_synthesis.tcl

+set_host_options -max_cores 8
+set top_module ahb_qspi_pads
+set report_path $env(SOCLABS_AHB_QSPI_DIR)/imp/ASIC/
+
+set search_path [list . $search_path /research/AAA/phys_ip_library/arm/tsmc/cln65lp/sc12_base_rvt/r0p0/db /home/dwn1c21/SoC-Labs/phys_ip/TSMC/65/CMOS/LP/IO2.5V/iolib/linear/tpdn65lpnv2od3_200a_FE/TSMCHOME/digital/Front_End/timing_power_noise/NLDM/tpdn65lpnv2od3_200a]
+
+set target_library "sc12_cln65lp_base_rvt_ss_typical_max_0p90v_125c.db tpdn65lpnv2od3wc1.db"
+set link_library "sc12_cln65lp_base_rvt_ss_typical_max_0p90v_125c.db tpdn65lpnv2od3wc1.db"
+
+source $env(SOCLABS_AHB_QSPI_DIR)/imp/ASIC/flist/dc_flist.tcl
+analyze -format verilog -lib WORK -define POWER_PINS $env(SOCLABS_AHB_QSPI_DIR)/pad_level/tsmc65nm/ahb_qspi_pads.v
+elaborate $top_module
+current_design $top_module
+
+link
+
+read_sdc ./ahb_qspi_constraints.sdc
+
+compile_ultra 
+
+write -format verilog -hierarchy -output $env(SOCLABS_AHB_QSPI_DIR)/imp/ASIC/top_ahb_qspi_gates.v
+write_sdf -version 2.1 $env(SOCLABS_AHB_QSPI_DIR)/imp/ASIC/top_ahb_qspi.sdf
+
+redirect [format "%s%s%s" $report_path $top_module _area.rep] { report_area }
+redirect [format "%s%s%s" $report_path $top_module _power.rep] { report_power }
+redirect [format "%s%s%s" $report_path $top_module _timing.rep] \
+  { report_timing -path full -max_paths 100 -nets -transition_time -capacitance -significant_digits 3 -nosplit}

flist/Top/ahb_QSPI_SIM.flist

@@ -3,3 +3,5 @@
 
 $(SOCLABS_AHB_QSPI_DIR)/logical/cache_models/generic/cache_ram.v
 $(ARM_IP_LIBRARY_PATH)/CG092/CG092-BU-50000-r2p0-00rel0/p_flash_cache_f0/logical/testbench/execution_tb/verilog/p_flash_cache_f0_sp_ram.v
+
+$(SOCLABS_AHB_QSPI_DIR)/pad_level/generic/ahb_qspi_pads.v
\ No newline at end of file

flist/Top/ahb_QSPI_SIM_GATES.flist

@@ -2,3 +2,7 @@
 $(SOCLABS_AHB_QSPI_DIR)/imp/ASIC/top_ahb_qspi_gates.v
 
 /home/dwn1c21/SoC-Labs/phys_ip/arm/tsmc/cln28ht/sc12mcpp140z_base_svt_c35/r2p0/verilog/sc12mcpp140z_cln28ht_base_svt_c35.v
+
+/research/AAA/phys_ip_library/arm/tsmc/cln65lp/sc12_base_rvt/r0p0/verilog/sc12_cln65lp_base_rvt.v
+/research/AAA/phys_ip_library/arm/tsmc/cln65lp/sc12_base_rvt/r0p0/verilog/sc12_cln65lp_base_rvt_udp.v
+/home/dwn1c21/SoC-Labs/phys_ip/TSMC/65/CMOS/LP/IO2.5V/iolib/linear/tpdn65lpnv2od3_200a_FE/TSMCHOME/digital/Front_End/verilog/tpdn65lpnv2od3_140b/tpdn65lpnv2od3.v
\ No newline at end of file

logical/apb_qspi_regs/logical/apb_qspi_regs.v

@@ -34,6 +34,8 @@ module apb_qspi_regs(
 
     output wire [7:0]           QSPI_CLK_DIV,
 
+    output wire                 IRQ_QSPI_FINISHED,
+
     // AHB Control Signals
     output wire [7:0]           AHB_QSPI_CMD,
     output wire [3:0]           AHB_QSPI_DUMMY_CYCLES
@@ -46,7 +48,9 @@ module apb_qspi_regs(
 //  QSPI_CONT_READ[24]             |  |----------------------------------------------------------------> QSPI_CONT_READ[24]
 //  QSPI_NO_CMD[25]                |-------------------------------------------------------------------> QSPI_NO_CMD[25]
 
-// reg1 Status
+// reg1 Status 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
+// QSPI_BUSY                                                                       |               |--> QSPI_BUSY
+// IRQ_CLR                                                                         |------------------> IRQ_CLR
 
 // reg2 SPI Commands 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
 //     QSPI_CMD [7:0]                                  |  |        |  |        |  |  | | | |----> QSPI_CMD [7:0]
@@ -68,6 +72,11 @@ module apb_qspi_regs(
 
 // reg13 QSPI_clk_div [7:0]
 
+reg qspi_finished;
+reg qspi_busy_last;
+assign IRQ_QSPI_FINISHED = qspi_finished;
+
+
 localparam [7:0] PIDR0 = 8'h59;
 localparam [7:0] PIDR1 = 8'h16;
 localparam [7:0] PIDR2 = 8'h15;
@@ -149,6 +158,8 @@ always @(posedge PCLK or negedge PRESETn) begin
         end
         if(QSPI_ENABLE_ACK)
             reg2[8]=1'b0;
+        if(reg1[8] & (~qspi_finished))
+            reg1[8]=1'b0;
         reg1[0] = QSPI_BUSY;
     end
 end
@@ -190,4 +201,20 @@ end
 assign PREADY =  1'b1; //(PSEL & PENABLE & PWRITE) | (PSEL & ~PWRITE);
 assign PSLVERR = 1'b0;
 
+//Interrupt generation
+always @(posedge PCLK or negedge PRESETn) begin
+    if(~PRESETn) begin
+        qspi_finished <= 1'b0;
+        qspi_busy_last <= 1'b0;
+    end else begin
+        qspi_busy_last <= QSPI_BUSY;
+
+        if(qspi_busy_last&(~QSPI_BUSY)) begin
+            qspi_finished <= 1'b1;
+        end else if((reg1[8])) begin
+            qspi_finished <= 1'b0;
+        end
+    end
+end
+
 endmodule

logical/top_ahb_qspi/logical/top_ahb_qspi.v

@@ -59,7 +59,9 @@ module top_ahb_qspi #(
     output wire                 QSPI_nCS,
     output wire [3:0]           QSPI_IO_o,
     input  wire [3:0]           QSPI_IO_i,
-    output wire [3:0]           QSPI_IO_e
+    output wire [3:0]           QSPI_IO_e,
+
+    output wire                 IRQ_QSPI_FINISHED
 );
 
 
@@ -364,6 +366,8 @@ apb_qspi_regs u_apb_qspi_regs(
     .QSPI_MODE_CODE(QSPI_MODE_CODE),
     .QSPI_NO_CMD(QSPI_NO_CMD),
     
+    .IRQ_QSPI_FINISHED(IRQ_QSPI_FINISHED),
+
     .QSPI_CLK_DIV(QSPI_CLK_DIV),
     .AHB_QSPI_CMD(AHB_QSPI_CMD),
     .AHB_QSPI_DUMMY_CYCLES(AHB_QSPI_DUMMY_CYCLES)

pad_level/generic/ahb_qspi_pads.v

+
+
+
+module ahb_qspi_pads (
+    input  wire                 HCLK,
+    input  wire                 HRESETn,
+    input  wire                 PCLK,
+    input  wire                 PRESETn,
+    // AHB Signals
+    input  wire [32-1:0]        HADDR,
+    input  wire [1:0]           HTRANS,
+    input  wire                 HWRITE,
+    input  wire [2:0]           HSIZE,
+    input  wire [2:0]           HBURST,
+    input  wire [3:0]           HPROT,
+    input  wire [32-1:0]        HWDATA,
+    input  wire                 HSELx,
+    output wire [32-1:0]        HRDATA,
+    input  wire                 HREADY,
+    output wire                 HREADYOUT,
+    output wire                 HRESP,
+
+    // APB Signals
+    input  wire [15:0]          PADDR,
+    input  wire [2:0]           PPROT,
+    input  wire                 PSEL,
+    input  wire                 PENABLE,
+    input  wire                 PWRITE,
+    input  wire [31:0]          PWDATA,
+    input  wire [3:0]           PSTRB,
+    output wire [31:0]          PRDATA,
+    output wire                 PREADY,
+    output wire                 PSLVERR,
+
+    // QSPI Signals
+    output wire                 QSPI_SCLK,
+    output wire                 QSPI_nCS,
+    inout  wire [3:0]           QSPI_IO,
+
+    output wire                 IRQ_QSPI_FINISHED
+);
+
+wire QSPI_SCLK_i;
+wire QSPI_nCS_i;
+wire [3:0] QSPI_IO_o;
+wire [3:0] QSPI_IO_i;
+wire [3:0] QSPI_IO_e;
+
+assign QSPI_IO[0] = QSPI_IO_e[0] ? QSPI_IO_o[0] : 1'bz;
+assign QSPI_IO[1] = QSPI_IO_e[1] ? QSPI_IO_o[1] : 1'bz;
+assign QSPI_IO[2] = QSPI_IO_e[2] ? QSPI_IO_o[2] : 1'bz;
+assign QSPI_IO[3] = QSPI_IO_e[3] ? QSPI_IO_o[3] : 1'bz;
+
+assign QSPI_IO_i[0] = QSPI_IO[0];
+assign QSPI_IO_i[1] = QSPI_IO[1];
+assign QSPI_IO_i[2] = QSPI_IO[2];
+assign QSPI_IO_i[3] = QSPI_IO[3];
+
+assign QSPI_SCLK = QSPI_SCLK_i;
+assign QSPI_nCS = QSPI_nCS_i;
+
+top_ahb_qspi u_top_ahb_qspi(
+    .HCLK(HCLK),
+    .HRESETn(HRESETn),
+    .PCLK(HCLK),
+    .PRESETn(HRESETn),
+
+    .HADDR(HADDR),
+    .HTRANS(HTRANS),
+    .HWRITE(HWRITE),
+    .HSIZE(HSIZE),
+    .HBURST(HBURST),
+    .HPROT(HPROT),
+    .HWDATA(HWDATA),
+    .HSELx(HSELx),
+    .HRDATA(HRDATA),
+    .HREADY(HREADY),
+    .HREADYOUT(HREADYOUT),
+    .HRESP(HRESP),
+
+    .PADDR(PADDR),
+    .PPROT(PPROT),
+    .PSEL(PSEL),
+    .PENABLE(PENABLE),
+    .PWRITE(PWRITE),
+    .PWDATA(PWDATA),
+    .PSTRB(PSTRB),
+    .PRDATA(PRDATA),
+    .PREADY(PREADY),
+    .PSLVERR(PSLVERR),
+
+    .QSPI_SCLK(QSPI_SCLK_i),
+    .QSPI_nCS(QSPI_nCS_i),
+    .QSPI_IO_o(QSPI_IO_o),
+    .QSPI_IO_i(QSPI_IO_i),
+    .QSPI_IO_e(QSPI_IO_e),
+
+    .IRQ_QSPI_FINISHED(IRQ_QSPI_FINISHED)
+);
+
+endmodule

pad_level/tsmc65nm/ahb_qspi_pads.v

+
+
+
+module ahb_qspi_pads (
+    input  wire                 HCLK,
+    input  wire                 HRESETn,
+    input  wire                 PCLK,
+    input  wire                 PRESETn,
+    // AHB Signals
+    input  wire [32-1:0]        HADDR,
+    input  wire [1:0]           HTRANS,
+    input  wire                 HWRITE,
+    input  wire [2:0]           HSIZE,
+    input  wire [2:0]           HBURST,
+    input  wire [3:0]           HPROT,
+    input  wire [32-1:0]        HWDATA,
+    input  wire                 HSELx,
+    output wire [32-1:0]        HRDATA,
+    input  wire                 HREADY,
+    output wire                 HREADYOUT,
+    output wire                 HRESP,
+
+    // APB Signals
+    input  wire [15:0]          PADDR,
+    input  wire [2:0]           PPROT,
+    input  wire                 PSEL,
+    input  wire                 PENABLE,
+    input  wire                 PWRITE,
+    input  wire [31:0]          PWDATA,
+    input  wire [3:0]           PSTRB,
+    output wire [31:0]          PRDATA,
+    output wire                 PREADY,
+    output wire                 PSLVERR,
+
+    // QSPI Signals
+    output wire                 QSPI_SCLK,
+    output wire                 QSPI_nCS,
+    inout  wire [3:0]           QSPI_IO,
+
+    output wire                 IRQ_QSPI_FINISHED
+);
+
+wire QSPI_SCLK_i;
+wire QSPI_nCS_i;
+wire [3:0] QSPI_IO_o;
+wire [3:0] QSPI_IO_i;
+wire [3:0] QSPI_IO_e;
+
+
+PRDW0408SCDG uPAD_QSPI_SCLK_o(
+    .IE(1'b0),
+    .C(),
+    .PE(1'b0),
+    .DS(1'b0),
+    .I(QSPI_SCLK_i),
+    .OEN(1'b0),
+    .PAD(QSPI_SCLK)
+);
+
+PRDW0408SCDG uPAD_QSPI_nCS_o(
+    .IE(1'b0),
+    .C(),
+    .PE(1'b0),
+    .DS(1'b0),
+    .I(QSPI_nCS_i),
+    .OEN(1'b0),
+    .PAD(QSPI_nCS)
+);
+
+
+PRDW0408SCDG uPAD_QSPI_IO_0(
+    .IE(~QSPI_IO_e[0]),
+    .C(QSPI_IO_i[0]),
+    .PE(1'b1),
+    .DS(1'b0),
+    .I(QSPI_IO_o[0]),
+    .OEN(~QSPI_IO_e[0]),
+    .PAD(QSPI_IO[0])
+);
+
+PRDW0408SCDG uPAD_QSPI_IO_1(
+    .IE(~QSPI_IO_e[1]),
+    .C(QSPI_IO_i[1]),
+    .PE(1'b1),
+    .DS(1'b0),
+    .I(QSPI_IO_o[1]),
+    .OEN(~QSPI_IO_e[1]),
+    .PAD(QSPI_IO[1])
+);
+
+PRDW0408SCDG uPAD_QSPI_IO_2(
+    .IE(~QSPI_IO_e[2]),
+    .C(QSPI_IO_i[2]),
+    .PE(1'b1),
+    .DS(1'b0),
+    .I(QSPI_IO_o[2]),
+    .OEN(~QSPI_IO_e[2]),
+    .PAD(QSPI_IO[2])
+);
+
+PRDW0408SCDG uPAD_QSPI_IO_3(
+    .IE(~QSPI_IO_e[3]),
+    .C(QSPI_IO_i[3]),
+    .PE(1'b1),
+    .DS(1'b0),
+    .I(QSPI_IO_o[3]),
+    .OEN(~QSPI_IO_e[3]),
+    .PAD(QSPI_IO[3])
+);
+
+
+top_ahb_qspi u_top_ahb_qspi(
+    .HCLK(HCLK),
+    .HRESETn(HRESETn),
+    .PCLK(HCLK),
+    .PRESETn(HRESETn),
+
+    .HADDR(HADDR),
+    .HTRANS(HTRANS),
+    .HWRITE(HWRITE),
+    .HSIZE(HSIZE),
+    .HBURST(HBURST),
+    .HPROT(HPROT),
+    .HWDATA(HWDATA),
+    .HSELx(HSELx),
+    .HRDATA(HRDATA),
+    .HREADY(HREADY),
+    .HREADYOUT(HREADYOUT),
+    .HRESP(HRESP),
+
+    .PADDR(PADDR),
+    .PPROT(PPROT),
+    .PSEL(PSEL),
+    .PENABLE(PENABLE),
+    .PWRITE(PWRITE),
+    .PWDATA(PWDATA),
+    .PSTRB(PSTRB),
+    .PRDATA(PRDATA),
+    .PREADY(PREADY),
+    .PSLVERR(PSLVERR),
+
+    .QSPI_SCLK(QSPI_SCLK_i),
+    .QSPI_nCS(QSPI_nCS_i),
+    .QSPI_IO_o(QSPI_IO_o),
+    .QSPI_IO_i(QSPI_IO_i),
+    .QSPI_IO_e(QSPI_IO_e),
+
+    .IRQ_QSPI_FINISHED(IRQ_QSPI_FINISHED)
+);
+
+endmodule

verif/cocotb/SST26VF064B.py

@@ -13,10 +13,22 @@ from cocotbext.ahb import AHBLiteMaster, AHBBus
 
 ID = 0x4326BF00
 
+async def wait_for_irq(dut, tb):
+    tb.log.info("Wait for IRQ")
+    while(dut.IRQ_QSPI_FINISHED.value==0):
+        await ClockCycles(dut.HCLK,1)
+    await tb.config_ahb_master.write(0x04,0x00000100)
+    await ClockCycles(dut.HCLK,2)
+    assert dut.IRQ_QSPI_FINISHED.value==0
+    data = await tb.config_ahb_master.read(0x04,4)
+    assert int(data[0]['data'],16)==0
+
 async def SPI_RESET(dut,tb):
     await tb.config_ahb_master.write(0x08, 0x00000066)
     await tb.config_ahb_master.write(0x08, 0x00000166)
 
+    await wait_for_irq(dut,tb)
+    
     data = await tb.config_ahb_master.read(0x04,4)
     while(int(data[0]['data'],16)&1):
         await ClockCycles(dut.HCLK,2)

verif/cocotb/ahb_qspi_cocotb.v

@@ -50,6 +50,8 @@ wire [31:0]          PRDATA;
 wire                 PREADY;
 wire                 PSLVERR;
 
+wire                IRQ_QSPI_FINISHED;
+
 cmsdk_ahb_to_apb #(
     .ADDRWIDTH(16),
     .REGISTER_RDATA(1),
@@ -88,11 +90,9 @@ cmsdk_ahb_to_apb #(
 
 wire QSPI_SCLK;
 wire QSPI_nCS;
-wire [3:0] QSPI_IO_o;
-wire [3:0] QSPI_IO_i;
-wire [3:0] QSPI_IO_e;
 wire [3:0] QSPI_IO;
-top_ahb_qspi u_top_ahb_qspi(
+
+ahb_qspi_pads u_ahb_qspi_pads(
     .HCLK(HCLK),
     .HRESETn(HRESETn),
     .PCLK(HCLK),
@@ -121,28 +121,21 @@ top_ahb_qspi u_top_ahb_qspi(
     .PRDATA(PRDATA),
     .PREADY(PREADY),
     .PSLVERR(PSLVERR),
+
     .QSPI_SCLK(QSPI_SCLK),
     .QSPI_nCS(QSPI_nCS),
-    .QSPI_IO_o(QSPI_IO_o),
-    .QSPI_IO_i(QSPI_IO_i),
-    .QSPI_IO_e(QSPI_IO_e)
+    .QSPI_IO(QSPI_IO),
+
+    .IRQ_QSPI_FINISHED(IRQ_QSPI_FINISHED)
+
 );
 
 `ifdef GATE_SIMS
 initial begin
-    $sdf_annotate("/home/dwn1c21/SoC-Labs/ahb_qspi/imp/ASIC/top_ahb_qspi.sdf", u_top_ahb_qspi);
+    $sdf_annotate("/home/dwn1c21/SoC-Labs/ahb_qspi/imp/ASIC/top_ahb_qspi.sdf", u_ahb_qspi_pads);
 end
 `endif
 
-assign QSPI_IO[0] = QSPI_IO_e[0] ? QSPI_IO_o[0] : 1'bz;
-assign QSPI_IO[1] = QSPI_IO_e[1] ? QSPI_IO_o[1] : 1'bz;
-assign QSPI_IO[2] = QSPI_IO_e[2] ? QSPI_IO_o[2] : 1'bz;
-assign QSPI_IO[3] = QSPI_IO_e[3] ? QSPI_IO_o[3] : 1'bz;
-
-assign QSPI_IO_i[0] = QSPI_IO[0];
-assign QSPI_IO_i[1] = QSPI_IO[1];
-assign QSPI_IO_i[2] = QSPI_IO[2];
-assign QSPI_IO_i[3] = QSPI_IO[3];
 
 sst26vf064b u_sst26vf064b(
     .SCK(QSPI_SCLK),

verif/cocotb/ahb_qspi_tests.py

@@ -202,12 +202,20 @@ async def QSPI_READ_TESTS(dut):
     QSPI_CTRL_REG = QSPI_CTRL_REG | (1<<8)
     await tb.config_ahb_master.write(0x00, QSPI_CTRL_REG)
 
+    QSPI_AHB_CMD_REG = (4<<12) + 0x0B
+    await tb.config_ahb_master.write(0x30, QSPI_AHB_CMD_REG)
+
+
     tb.log.info("Configure Cache")
     CACHE_STATUS_tmp = await tb.config_ahb_master.read(CACHE_CONFIG_ADDR+0x04,4)
     CACHE_STATUS = int(CACHE_STATUS_tmp[0]['data'],16)
     assert CACHE_STATUS==0  
     
-    await tb.config_ahb_master.write(CACHE_CONFIG_ADDR, 0x21)
+    await tb.config_ahb_master.write(CACHE_CONFIG_ADDR, 0x1)
+
+    CACHE_CONFIG_tmp = await tb.config_ahb_master.read(CACHE_CONFIG_ADDR,4)
+    CACHE_CONFIG = int(CACHE_CONFIG_tmp[0]['data'],16)
+    assert CACHE_CONFIG == 0x1
 
     CACHE_STATUS_tmp = await tb.config_ahb_master.read(CACHE_CONFIG_ADDR+0x04,4)
     CACHE_STATUS = int(CACHE_STATUS_tmp[0]['data'],16)
@@ -220,6 +228,7 @@ async def QSPI_READ_TESTS(dut):
     tb.log.info("Read %d x 16-bytes over AHB (uncached)",n_reads)
     start_time_uncached = cocotb.utils.get_sim_time(units='ns')
     for i in range(0,n_reads*4):
+        tb.log.info("Read %d ",i)
         rdata = await tb.data_ahb_master.read(i*4 + base_addr,4)
         assert int(rdata[0]['data'],16)==data[i%4]
     end_time_uncached = cocotb.utils.get_sim_time(units='ns')