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Commit d3d58a30 authored by dwn1c21's avatar dwn1c21
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Update module hierarchy

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flist/IP/CG092_cache.flist 0 → 100644
+ 18
− 0
View file @ d3d58a30
// ============= Verilog library extensions ===========
+libext+.v+.vlib
+incdir+/Users/danielnewbrook/Documents/SoCLabs/AAA/ip_dir/CG092-BU-50000-r2p0-00rel0/p_flash_cache_f0/logical/p_flash_cache_f0/verilog
/Users/danielnewbrook/Documents/SoCLabs/AAA/ip_dir/CG092-BU-50000-r2p0-00rel0/p_flash_cache_f0/logical/p_flash_cache_f0/verilog/p_flash_cache_f0_bus_logic.v
/Users/danielnewbrook/Documents/SoCLabs/AAA/ip_dir/CG092-BU-50000-r2p0-00rel0/p_flash_cache_f0/logical/p_flash_cache_f0/verilog/p_flash_cache_f0_mrb.v
/Users/danielnewbrook/Documents/SoCLabs/AAA/ip_dir/CG092-BU-50000-r2p0-00rel0/p_flash_cache_f0/logical/p_flash_cache_f0/verilog/p_flash_cache_f0_core.v
/Users/danielnewbrook/Documents/SoCLabs/AAA/ip_dir/CG092-BU-50000-r2p0-00rel0/p_flash_cache_f0/logical/p_flash_cache_f0/verilog/p_flash_cache_f0.v
/Users/danielnewbrook/Documents/SoCLabs/AAA/ip_dir/CG092-BU-50000-r2p0-00rel0/p_flash_cache_f0/logical/p_flash_cache_f0/verilog/p_flash_cache_f0_reg_block.v
/Users/danielnewbrook/Documents/SoCLabs/AAA/ip_dir/CG092-BU-50000-r2p0-00rel0/p_flash_cache_f0/logical/models/cells/generic/p_flash_cache_f0_capt_sync.v
/Users/danielnewbrook/Documents/SoCLabs/AAA/ip_dir/CG092-BU-50000-r2p0-00rel0/p_flash_cache_f0/logical/models/cells/generic/cdc_capt_sync.v
/Users/danielnewbrook/Documents/SoCLabs/AAA/ip_dir/CG092-BU-50000-r2p0-00rel0/p_flash_cache_f0/logical/models/modules/generic/p_flash_cache_f0_static_reg.v
/Users/danielnewbrook/Documents/SoCLabs/AAA/ip_dir/CG092-BU-50000-r2p0-00rel0/p_flash_cache_f0/logical/models/modules/generic/static_reg.v
flist/Top/ahb_QSPI.flist
+ 8
− 1
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$(SOCLABS_AHB_QSPI_DIR)/logical/top_ahb_qspi/logical/top_ahb_qspi.v
\ No newline at end of file
$(SOCLABS_AHB_QSPI_DIR)/logical/top_ahb_qspi/logical/top_ahb_qspi.sv
$(SOCLABS_AHB_QSPI_DIR)/logical/apb_qspi_regs/logical/apb_qspi_regs.sv
$(SOCLABS_AHB_QSPI_DIR)/logical/ahb_qspi_interface/logical/ahb_qspi_interface.sv
$(SOCLABS_AHB_QSPI_DIR)/logical/qspi_controller/logical/qspi_controller.sv
$(SOCLABS_AHB_QSPI_DIR)/logical/cache_subsytem/logical/cache_subsystem.v
-f $(SOCLABS_AHB_QSPI_DIR)/flist/IP/CG092_cache.flist
\ No newline at end of file
flist/Top/ahb_QSPI_SIM.flist 0 → 100644
+ 2
− 0
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-f $(SOCLABS_AHB_QSPI_DIR)/flist/Top/ahb_QSPI.flist
-f $(SOCLABS_AHB_QSPI_DIR)/flist/VIP/ahb_QSPI_VIP.flist
\ No newline at end of file
flist/VIP/ahb_QSPI_VIP.flist 0 → 100644
+ 1
− 0
View file @ d3d58a30
/Users/danielnewbrook/Documents/SoCLabs/AAA/ip_dir/BP210-BU-00000-r1p1-00rel0/logical/cmsdk_ahb_to_apb/verilog/cmsdk_ahb_to_apb.v
flows/makefile.simulate
+ 2
− 0
View file @ d3d58a30
......@@ -20,6 +20,8 @@ else ifeq ($(SIMULATOR),xm)
COCOTB_SIMULATOR := xcelium
else ifeq ($(SIMULATOR),vcs)
COCOTB_SIMULATOR := vcs
else ifeq ($(SIMULATOR), icarus)
COCOTB_SIMULATOR := icarus
endif
# Cocotb GUI Variable
......
logical/ahb_qspi_interface/logical/ahb_qspi_interface.sv 0 → 100644
+ 77
− 0
View file @ d3d58a30
module ahb_qspi_interface #(
parameter ADDR_W = 32,
parameter DATA_W = 32
)(
input wire HCLK,
input wire HRESETn,
// AHB Signals
input wire [ADDR_W-1:0] HADDR,
input wire [1:0] HTRANS,
input wire HWRITE,
input wire [2:0] HSIZE,
input wire [2:0] HBURST,
input wire [3:0] HPROT,
input wire [DATA_W-1:0] HWDATA,
input wire HSELx,
output wire [DATA_W-1:0] HRDATA,
input wire HREADY,
output wire HREADYOUT,
output wire HRESP
);
assign HREADYOUT = 1'b0;
assign HRESP = 1'b0;
// AHB FSM
enum {IDLE, WAIT_READ, WAIT_WRITE, WRITE, READ} current_state, next_state;
// AHB lite last regs
reg last_HSEL;
reg [31:0] last_HADDR;
reg last_HWRITE;
reg [1:0] last_HTRANS;
//
reg qspi_ready;
always @(posedge HCLK or negedge HRESETn) begin
if(~HRESETn) begin
last_HSEL <= 1'b0;
last_HADDR <= 32'd0;
last_HWRITE <= 1'b0;
last_HTRANS <= 2'b00;
current_state <= IDLE;
qspi_ready <= 1'b0;
end else begin
last_HSEL <= HSELx;
last_HADDR <= HADDR;
last_HWRITE <= HWRITE;
last_HTRANS <= HTRANS;
current_state <= next_state;
end
end
always @(*) begin
next_state = IDLE;
case(current_state)
IDLE: if(HSELx & HWRITE & ~qspi_ready)
next_state = WAIT_WRITE;
else if(HSELx & ~qspi_ready)
next_state = WAIT_READ;
WAIT_WRITE: if(qspi_ready)
next_state = WRITE;
else
next_state = WAIT_WRITE;
WAIT_READ: if(qspi_ready)
next_state = READ;
else
next_state = WAIT_READ;
READ: next_state = IDLE;
WRITE: next_state = IDLE;
endcase
end
endmodule
\ No newline at end of file
logical/apb_qspi_regs/logical/apb_qspi_regs.sv 0 → 100644
+ 48
− 0
View file @ d3d58a30
module apb_qspi_regs(
// APB Signals
input wire PCLK,
input wire PRESETn,
input wire [11:2] PADDR,
input wire [2:0] PPROT,
input wire PSEL,
input wire PENABLE,
input wire PWRITE,
input wire [31:0] PWDATA,
input wire [3:0] PSTRB,
output reg [31:0] PRDATA,
output wire PREADY,
output wire PSLVERR
);
// Registers
reg [31:0] reg0;
reg [31:0] reg1;
always @(posedge PCLK or negedge PRESETn) begin
if(~PRESETn) begin
reg0 = 32'd0;
reg1 = 32'd0;
end else begin
if(PSEL & PENABLE & PWRITE) begin
case(PADDR)
10'h000: reg0 = PWDATA;
10'h001: reg1 = PWDATA;
endcase
end
end
end
always @(PCLK, PADDR) begin
if(PCLK) begin
case(PADDR)
10'h000: PRDATA = reg0;
10'h001: PRDATA = reg1;
endcase
end
end
assign PREADY = 1'b1; //(PSEL & PENABLE & PWRITE) | (PSEL & ~PWRITE);
assign PSLVERR = 1'b0;
endmodule
\ No newline at end of file
logical/cache_subsytem/logical/cache_subsystem.v 0 → 100644
+ 146
− 0
View file @ d3d58a30
module cache_subsystem(
input wire HCLK,
input wire HRESETn,
// APB
input wire PCLKG,
input wire [11:0] PADDR,
input wire [31:0] PWDATA,
input wire PWRITE,
input wire PSEL,
input wire PENABLE,
input wire [3:0] PSTRB,
input wire [2:0] PPROT,
output wire [31:0] PRDATA,
output wire PSLVERR,
output wire PREADY,
// AHB Subordinate
input wire HSELS, // Device select
input wire [21:0] HADDRS, // Address
input wire [2:0] HBURSTS, // Burst Type - Not used!
input wire HMASTLOCKS, // Master Lock - Not used!
input wire [1:0] HTRANSS, // Transfer control
input wire [2:0] HSIZES, // Transfer size
input wire [3:0] HPROTS, // Transfer Protection
input wire HWRITES, // Write control
input wire [31:0] HWDATAS, // Write data
input wire HREADYS, // Transfer phase done
input wire HMASTERS, // When 1 indicate a debug access
output wire HREADYOUTS, // Device ready
output wire [31:0] HRDATAS, // Read data output
output wire HRESPS,
// AHB Manager
output wire HSELM, // Device select
output wire [21:0] HADDRM, // Address
output wire [2:0] HBURSTM, // Burst Type - Not used (tied to 0)!
output wire HMASTLOCKM, // Master Lock - Not used (tied to 0)!
output wire [1:0] HTRANSM, // Transfer control
output wire [2:0] HSIZEM, // Transfer size
output wire [3:0] HPROTM, // Transfer Protection
output wire HWRITEM, // Write control
output wire [127:0] HWDATAM, // Write data
output wire HREADYM, // Transfer phase done
input wire HREADYOUTM, // Device ready
input wire [127:0] HRDATAM, // Read data output
input wire HRESPM, // Error response
output wire IRQ,
output wire CACHEMISS,
output wire CACHEHIT
);
p_flash_cache_f0 #(
.AW(22),
.CW(12),
.CACHE_WAY(2),
.RESET_ALL_REGS(0),
.GEN_STAT_LOGIC(1),
.LINEW(4)
) u_cache_controller(
.HCLK(HCLK),
.HRESETn(HRESETn),
// APB Interface
.PCLKG(PCLKG),
.PADDR(PADDR),
.PWDATA(PWDATA),
.PWRITE(PWRITE),
.PSEL(PSEL),
.PENABLE(PENABLE),
.PSTRB(PSTRB),
.PPROT(PPROT),
.PRDATA(PRDATA),
.PSLVERR(PSLVERR),
.PREADY(PREADY),
// AHB Subordinate
.HSELS(HSELS),
.HADDRS(HADDRS),
.HBURSTS(HBURSTS),
.HMASTLOCKS(HMASTLOCKS),
.HTRANSS(HTRANSS),
.HSIZES(HSIZES),
.HPROTS(HPROTS),
.HWRITES(HWRITES),
.HWDATAS(HWDATAS),
.HREADYS(HREADYS),
.HMASTERS(HMASTERS),
.HREADYOUTS(HREADYOUTS),
.HRDATAS(HRDATAS),
.HRESPS(HRESPS),
// CACHE RAM POWER UP
.RAMPWRUPREQ(),
.RAMPWRUPACK(),
// TAG RAM way 0
.RAMTAG0ADDR(),
.RAMTAG0WE(),
.RAMTAG0RD(),
.RAMTAG0CS(),
.RAMTAG0WDATA(),
.RAMTAG0RDATA(),
// Data RAM way 0
.RAMCLD0ADDR(),
.RAMCLD0WE(),
.RAMCLD0RD(),
.RAMCLD0CS(),
.RAMCLD0WDATA(),
.RAMCLD0RDATA(),
// TAG RAM way 1
.RAMTAG1ADDR(),
.RAMTAG1WE(),
.RAMTAG1RD(),
.RAMTAG1CS(),
.RAMTAG1WDATA(),
.RAMTAG1RDATA(),
// Data RAM Way 1
.RAMCLD1ADDR(),
.RAMCLD1WE(),
.RAMCLD1RD(),
.RAMCLD1CS(),
.RAMCLD1WDATA(),
.RAMCLD1RDATA(),
// AHB Manager
.HSELM(HSELM),
.HADDRM(HADDRM),
.HBURSTM(HBURSTM),
.HMASTLOCKM(HMASTLOCKM),
.HTRANSM(HTRANSM),
.HSIZEM(HSIZEM),
.HPROTM(HPROTM),
.HWRITEM(HWRITEM),
.HWDATAM(HWDATAM),
.HREADYM(HREADYM),
.HREADYOUTM(HREADYOUTM),
.HRDATAM(HRDATAM),
.HRESPM(HRESPM),
.IRQ(IRQ),
.CACHEMISS(CACHEMISS),
.CACHEHIT(CACHEHIT)
);
endmodule
\ No newline at end of file
logical/qspi_controller/logical/qspi_controller.sv 0 → 100644
+ 46
− 0
View file @ d3d58a30
module qspi_controller (
input wire HCLK,
input wire HRESETn,
input wire [7:0] QSPI_CLK_DIV,
input wire [1:0] QSPI_SPI_MODE, // {CPOL, CPHA}
input wire [7:0] QSPI_CMD,
input wire [23:0] QSPI_ADDR,
input wire [31:0] QSPI_WDATA,
output wire [31:0] QSPI_RDATA,
// QSPI Interface
output wire QSPI_SCLK
);
reg [7:0] QSPI_CLK_DIV_COUNTER;
wire QSPI_ACTIVE;
reg QSPI_SCLK_reg;
assign QSPI_ACTIVE = 1'b1;
assign QSPI_SCLK = (QSPI_CLK_DIV==8'h00) ? HCLK : QSPI_SCLK_reg;
// Clock Divider for SCLK
always @(posedge HCLK or negedge HRESETn) begin
if(~HRESETn) begin
QSPI_CLK_DIV_COUNTER<=8'h00;
QSPI_SCLK_reg <= 1'b0;
end else begin
if(QSPI_ACTIVE) begin
if(QSPI_CLK_DIV!=8'h00) begin
if(QSPI_CLK_DIV_COUNTER==QSPI_CLK_DIV-1'b1) begin
QSPI_CLK_DIV_COUNTER <= 8'h00;
end else begin
QSPI_SCLK_reg <= ~QSPI_SCLK_reg;
QSPI_CLK_DIV_COUNTER <= QSPI_CLK_DIV_COUNTER + 1'b1;
end
end else begin
QSPI_SCLK_reg <= QSPI_SPI_MODE[1];
end
end else begin
QSPI_SCLK_reg <= QSPI_SPI_MODE[1];
end
end
end
endmodule
\ No newline at end of file
logical/top_ahb_qspi/logical/top_ahb_qspi.v → logical/top_ahb_qspi/logical/top_ahb_qspi.sv
+ 96
− 0
View file @ d3d58a30
module top_ahb_qspi #(
parameter ADDR_W = 16,
parameter ADDR_W = 32,
parameter DATA_W = 32
)(
input wire HCLK,
input wire HRESETn,
input wire PCLK,
input wire PRESETn,
// AHB Signals
input wire [ADDR_W-1:0] HADDR,
input wire [1:0] HTRANS,
......@@ -21,6 +22,18 @@ module top_ahb_qspi #(
output wire HREADYOUT,
output wire HRESP,
// APB Signals
input wire [11:2] PADDR,
input wire [2:0] PPROT,
input wire PSEL,
input wire PENABLE,
input wire PWRITE,
input wire [31:0] PWDATA,
input wire [3:0] PSTRB,
output wire [31:0] PRDATA,
output wire PREADY,
output wire PSLVERR,
// QSPI Signals
output wire QSPI_SCLK,
output wire QSPI_nCS,
......@@ -29,5 +42,55 @@ module top_ahb_qspi #(
output wire [3:0] QSPI_IO_e
);
cache_subsystem u_cache_subsystem(
);
apb_qspi_regs u_apb_qspi_regs(
.PCLK(PCLK),
.PRESETn(PRESETn),
.PADDR(PADDR),
.PPROT(PPROT),
.PSEL(PSEL),
.PENABLE(PENABLE),
.PWRITE(PWRITE),
.PWDATA(PWDATA),
.PSTRB(PSTRB),
.PRDATA(PRDATA),
.PREADY(PREADY),
.PSLVERR(PSLVERR)
);
ahb_qspi_interface #(
.ADDR_W(ADDR_W),
.DATA_W(DATA_W)
) u_ahb_qspi_interface (
.HCLK(HCLK),
.HRESETn(HRESETn),
.HADDR(HADDR),
.HTRANS(HTRANS),
.HWRITE(HWRITE),
.HSIZE(HSIZE),
.HBURST(HBURST),
.HPROT(HPROT),
.HWDATA(HWDATA),
.HSELx(HSELx),
.HRDATA(HRDATA),
.HREADY(HREADY),
.HREADYOUT(HREADYOUT),
.HRESP(HRESP)
);
qspi_controller u_qspi_controller(
.HCLK(HCLK),
.HRESETn(HRESETn),
.QSPI_CLK_DIV(8'h02),
.QSPI_SPI_MODE(2'b11),
.QSPI_CMD(),
.QSPI_ADDR(),
.QSPI_WDATA(),
.QSPI_RDATA(),
.QSPI_SCLK(QSPI_SCLK)
);
endmodule
\ No newline at end of file
make.cfg 0 → 100644
+ 1
− 0
View file @ d3d58a30
BP210_DIR ?=
\ No newline at end of file
makefile
+ 5
− 1
View file @ d3d58a30
include $(SOCLABS_AHB_QSPI_DIR)/make.cfg
#-------------------------------------
# - Commonly Overloaded Variables
#-------------------------------------
......@@ -15,8 +17,10 @@ SIM_DIR ?= $(SIM_TOP_DIR)
ifeq ($(ASIC),yes)
DESIGN_VC ?= $(SOCLABS_AHB_QSPI_DIR)/flist/Top/ahb_QSPI_ASIC.flist
else
DESIGN_VC ?= $(SOCLABS_AHB_QSPI_DIR)/flist/Top/ahb_QSPI.flist
DESIGN_VC ?= $(SOCLABS_AHB_QSPI_DIR)/flist/Top/ahb_QSPI_SIM.flist
endif
#Include flows
include ./flows/makefile.simulate
export BP210_DIR
\ No newline at end of file
verif/cocotb/ahb_qspi_cocotb.v
+ 102
− 25
View file @ d3d58a30
......@@ -5,38 +5,115 @@ module ahb_qspi_cocotb(
input wire HRESETn,
// AHB Signals
input wire [32-1:0] cocotb_HADDR,
input wire [1:0] cocotb_HTRANS,
input wire cocotb_HWRITE,
input wire [2:0] cocotb_HSIZE,
input wire [2:0] cocotb_HBURST,
input wire [3:0] cocotb_HPROT,
input wire [32-1:0] cocotb_HWDATA,
input wire cocotb_HSELx,
output wire [32-1:0] cocotb_HRDATA,
input wire cocotb_HREADY,
output wire cocotb_HREADYOUT,
output wire cocotb_HRESP
input wire [32-1:0] config_HADDR,
input wire [1:0] config_HTRANS,
input wire config_HWRITE,
input wire [2:0] config_HSIZE,
input wire [2:0] config_HBURST,
input wire [3:0] config_HPROT,
input wire [32-1:0] config_HWDATA,
input wire config_HSEL,
output wire [32-1:0] config_HRDATA,
input wire config_HREADY_IN,
output wire config_HREADY,
output wire config_HRESP,
input wire [32-1:0] data_HADDR,
input wire [1:0] data_HTRANS,
input wire data_HWRITE,
input wire [2:0] data_HSIZE,
input wire [2:0] data_HBURST,
input wire [3:0] data_HPROT,
input wire [32-1:0] data_HWDATA,
input wire data_HSEL,
output wire [32-1:0] data_HRDATA,
input wire data_HREADY_IN,
output wire data_HREADY,
output wire data_HRESP
);
initial
begin
$dumpfile("ahb_qspi.vcd");
$dumpvars;
end
top_ahb_qspi u_top_ahb_qspi(
wire [11:0] PADDR;
wire [2:0] PPROT;
wire PSEL;
wire PENABLE;
wire PWRITE;
wire [31:0] PWDATA;
wire [3:0] PSTRB;
wire [31:0] PRDATA;
wire PREADY;
wire PSLVERR;
cmsdk_ahb_to_apb #(
.ADDRWIDTH(12),
.REGISTER_RDATA(1),
.REGISTER_WDATA(0)
) u_cmsdk_ahb_to_apb (
.HCLK(HCLK),
.HRESETn(HRESETn),
.PCLKEN(1'b1),
.HSEL(config_HSEL),
.HADDR(config_HADDR[11:0]),
.HTRANS(config_HTRANS),
.HSIZE(config_HSIZE),
.HPROT(config_HPROT),
.HWRITE(config_HWRITE),
.HREADY(config_HREADY_IN),
.HWDATA(config_HWDATA),
.HREADYOUT(config_HREADY),
.HRDATA(config_HRDATA),
.HRESP(config_HRESP),
.HADDR(cocotb_HADDR),
.HTRANS(cocotb_HTRANS),
.HWRITE(cocotb_HWRITE),
.HSIZE(cocotb_HSIZE),
.HBURST(cocotb_HBURST),
.HPROT(cocotb_HPROT),
.HWDATA(cocotb_HWDATA),
.HSELx(cocotb_HSELx),
.HRDATA(cocotb_HRDATA),
.HREADY(cocotb_HREADY),
.HREADYOUT(cocotb_HREADYOUT),
.HRESP(cocotb_HRESP),
.PADDR(PADDR),
.PENABLE(PENABLE),
.PWRITE(PWRITE),
.PSTRB(PSTRB),
.PPROT(PPROT),
.PWDATA(PWDATA),
.PSEL(PSEL),
.APBACTIVE(),
.PRDATA(PRDATA),
.PREADY(PREADY),
.PSLVERR(PSLVERR)
);
top_ahb_qspi u_top_ahb_qspi(
.HCLK(HCLK),
.HRESETn(HRESETn),
.PCLK(HCLK),
.PRESETn(HRESETn),
.HADDR(data_HADDR),
.HTRANS(data_HTRANS),
.HWRITE(data_HWRITE),
.HSIZE(data_HSIZE),
.HBURST(data_HBURST),
.HPROT(data_HPROT),
.HWDATA(data_HWDATA),
.HSELx(data_HSEL),
.HRDATA(data_HRDATA),
.HREADY(data_HREADY),
.HREADYOUT(data_HREADY),
.HRESP(data_HRESP),
.PADDR(PADDR[11:2]),
.PPROT(PPROT),
.PSEL(PSEL),
.PENABLE(PENABLE),
.PWRITE(PWRITE),
.PWDATA(PWDATA),
.PSTRB(PSTRB),
.PRDATA(PRDATA),
.PREADY(PREADY),
.PSLVERR(PSLVERR),
.QSPI_SCLK(),
.QSPI_nCS(),
.QSPI_IO_o(),
......
verif/cocotb/ahb_qspi_tests.py
+ 18
− 3
View file @ d3d58a30
......@@ -11,15 +11,21 @@ from cocotb.regression import TestFactory
from cocotbext.ahb import AHBLiteMaster, AHBBus
FREQ = 240
CONFIG_ADDR = 0x0
DATA_ADDR = 0x10000000
class TB:
def __init__(self,dut):
self.dut = dut
self.log = logging.getLogger("cocotb.tb")
self.log.setLevel(logging.DEBUG)
cocotb.start_soon(Clock(dut.HCLK, 4.166, units="ns").start())
self.config_ahb_master = AHBLiteMaster(AHBBus.from_prefix(dut,"config", optional_signals = {"hsel":"HSEL", "hready_in":"HREADY_IN", "hburst":"HBURST", "hprot":"HPROT"}), dut.HCLK, dut.HRESETn)
self.data_ahb_master = AHBLiteMaster(AHBBus.from_prefix(dut,"data", optional_signals = {"hsel":"HSEL", "hready_in":"HREADY_IN", "hburst":"HBURST", "hprot":"HPROT"}), dut.HCLK, dut.HRESETn)
cocotb.start_soon(Clock(dut.HCLK, 10, units="ns").start())
self.ahb_master = AHBLiteMaster(AHBBus.from_prefix(dut,"cocotb"), dut.HCLK, dut.HRESETn)
async def cycle_reset(self):
self.dut.HRESETn.setimmediatevalue(0)
await ClockCycles(self.dut.HCLK,20)
......@@ -31,4 +37,13 @@ async def AHB_QSPI_1(dut):
tb = TB(dut)
await tb.cycle_reset()
await tb.ahb_master.write(0x00,0x15)
\ No newline at end of file
await tb.config_ahb_master.write(0x00,0xBEEFBEEF)
await tb.config_ahb_master.write(0x04,0xCAFECAFE)
await ClockCycles(dut.HCLK,2)
data = await tb.config_ahb_master.read(0x00,4)
await ClockCycles(dut.HCLK,2)
print(data)
data = await tb.config_ahb_master.read(0x00,4)
print(data)
data = await tb.config_ahb_master.read(0x04,4)
assert int(data[0]['data'],16) == 0xcafecafe
0% or .
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