V1.0 tested with megasoc and working but inefficient

flist/IP/CG092_cache.flist

@@ -2,6 +2,7 @@
 // ============= Verilog library extensions ===========
 +libext+.v+.vlib
 
++incdir+$(ARM_IP_LIBRARY_PATH)/CG092/CG092-BU-50000-r2p0-00rel0/p_flash_cache_f0/logical/p_flash_cache_f0/verilog
 
 $(ARM_IP_LIBRARY_PATH)/CG092/CG092-BU-50000-r2p0-00rel0/p_flash_cache_f0/logical/p_flash_cache_f0/verilog/p_flash_cache_f0_bus_logic.v
 $(ARM_IP_LIBRARY_PATH)/CG092/CG092-BU-50000-r2p0-00rel0/p_flash_cache_f0/logical/p_flash_cache_f0/verilog/p_flash_cache_f0_mrb.v

flist/Top/ahb_QSPI.flist

@@ -2,9 +2,9 @@
 
 $(SOCLABS_AHB_QSPI_DIR)/logical/top_ahb_qspi/logical/top_ahb_qspi.v
 $(SOCLABS_AHB_QSPI_DIR)/logical/apb_qspi_regs/logical/apb_qspi_regs.v
-$(SOCLABS_AHB_QSPI_DIR)/logical/ahb_qspi_interface/logical/ahb_qspi_interface.v
+$(SOCLABS_AHB_QSPI_DIR)/logical/ahb_qspi_interface/logical/ahb_qspi_interface.sv
 
-$(SOCLABS_AHB_QSPI_DIR)/logical/qspi_controller/logical/qspi_controller.v
+$(SOCLABS_AHB_QSPI_DIR)/logical/qspi_controller/logical/qspi_controller.sv
 $(SOCLABS_AHB_QSPI_DIR)/logical/qspi_controller/logical/qspi_controller_mux.v
 
 $(SOCLABS_AHB_QSPI_DIR)/logical/cache_subsytem/logical/cache_subsystem.v

flows/makefile.lint

@@ -10,7 +10,6 @@
 #-----------------------------------------------------------------------------
 
 # Include Lint Checks
-include $(SOCLABS_SOCTOOLS_FLOW_DIR)/resources/hal/makefile.hal_checks
 
 # Lint-related Directories
 LINT_DIR = $(SOCLABS_AHB_QSPI_DIR)/lint/ahb_qspi

logical/ahb_qspi_interface/logical/ahb_qspi_interface.v → logical/ahb_qspi_interface/logical/ahb_qspi_interface.sv

@@ -26,7 +26,7 @@ module ahb_qspi_interface #(
     output wire                 AHB_QSPI_WRITE,
     output wire                 AHB_QSPI_ADDR_EN,
     output wire [3:0]           AHB_QSPI_DUMMY_CYCLES,
-    output wire [3:0]           AHB_QSPI_N_RW_BYTES,
+    output reg [3:0]            AHB_QSPI_N_RW_BYTES,
     output reg  [21:0]          AHB_QSPI_ADDR,
     output wire [127:0]         AHB_QSPI_WDATA,
 
@@ -38,15 +38,21 @@ module ahb_qspi_interface #(
 );
 
 assign HRESP = 1'b0;
-
 assign AHB_QSPI_CMD = 8'h0B;
 assign AHB_QSPI_ADDR_EN = 1'b1;
 assign AHB_QSPI_DUMMY_CYCLES = 4'h4;
-assign AHB_QSPI_N_RW_BYTES = 4'hF;
 assign AHB_QSPI_READ=1'b1;
 assign AHB_QSPI_WRITE=1'b0;
 assign AHB_QSPI_WDATA = HWDATA;
 
+
+wire [31:0] AHB_QSPI_RDATA_W0 = {AHB_QSPI_RDATA[71:64],AHB_QSPI_RDATA[79:72],AHB_QSPI_RDATA[87:80],AHB_QSPI_RDATA[95:88]}; //AHB_QSPI_RDATA[95:64];
+wire [31:0] AHB_QSPI_RDATA_W1 = {AHB_QSPI_RDATA[39:32], AHB_QSPI_RDATA[47:40], AHB_QSPI_RDATA[55:48], AHB_QSPI_RDATA[63:56]}; //AHB_QSPI_RDATA[63:32]; //94000049
+wire [31:0] AHB_QSPI_RDATA_W2 = {AHB_QSPI_RDATA[7:0], AHB_QSPI_RDATA[15:8], AHB_QSPI_RDATA[23:16], AHB_QSPI_RDATA[31:24]};
+wire [31:0] AHB_QSPI_RDATA_W3 = {AHB_QSPI_RDATA[103:96],AHB_QSPI_RDATA[111:104],AHB_QSPI_RDATA[119:112],AHB_QSPI_RDATA[127:120]};//AHB_QSPI_RDATA[127:96];
+
+wire [127:0] AHB_QSPI_RDATA_i = {AHB_QSPI_RDATA_W3,AHB_QSPI_RDATA_W0, AHB_QSPI_RDATA_W1, AHB_QSPI_RDATA_W2};
+
 // AHB FSM
 enum {IDLE, WAIT_READ, WAIT_WRITE, WRITE, READ} current_state, next_state;
 
@@ -55,6 +61,7 @@ reg                 last_HSEL;
 reg [ADDR_W-1:0]    last_HADDR;
 reg                 last_HWRITE;
 reg [1:0]           last_HTRANS;
+reg [2:0]           last_HSIZE;
 
 // 
 reg         qspi_ready;
@@ -68,6 +75,7 @@ always @(posedge HCLK or negedge HRESETn) begin
         last_HADDR  <= {ADDR_W{1'b0}};
         last_HWRITE <= 1'b0;
         last_HTRANS <= 2'b00;
+        last_HSIZE  <= 3'h0;
 
         current_state <= IDLE;
     end else begin 
@@ -75,6 +83,7 @@ always @(posedge HCLK or negedge HRESETn) begin
         last_HADDR  <= HADDR;
         last_HWRITE <= HWRITE;
         last_HTRANS <= HTRANS;
+        last_HSIZE  <= HSIZE;
 
         current_state <= next_state;
     end
@@ -82,13 +91,33 @@ end
 
 always @(*) begin
     next_state = IDLE;
+
     case(current_state)
         IDLE:           if(HTRANS==2'b00)
                             next_state = IDLE;
-                        else if(HSELx & HWRITE & ~qspi_ready)
+                        else if(HSELx & HWRITE & ~qspi_ready) begin
+                            case(HSIZE)
+                                3'b000: AHB_QSPI_N_RW_BYTES = 4'hF;
+                                3'b001: AHB_QSPI_N_RW_BYTES = 4'hF;
+                                3'b010: AHB_QSPI_N_RW_BYTES = 4'hF;
+                                3'b011: AHB_QSPI_N_RW_BYTES = 4'hF;
+                                3'b100: AHB_QSPI_N_RW_BYTES = 4'hF;
+                                default: AHB_QSPI_N_RW_BYTES = 4'hF;
+                            endcase
+
                             next_state = WAIT_WRITE;
-                        else if(HSELx & ~qspi_ready)
+                        end
+                        else if(HSELx & ~qspi_ready) begin
+                            case(HSIZE)
+                                3'b000: AHB_QSPI_N_RW_BYTES = 4'hF;
+                                3'b001: AHB_QSPI_N_RW_BYTES = 4'hF;
+                                3'b010: AHB_QSPI_N_RW_BYTES = 4'hF;
+                                3'b011: AHB_QSPI_N_RW_BYTES = 4'hF;
+                                3'b100: AHB_QSPI_N_RW_BYTES = 4'hF;
+                                default: AHB_QSPI_N_RW_BYTES = 4'hF;
+                            endcase
                             next_state = WAIT_READ;
+                        end
         WAIT_WRITE:     if(qspi_ready)
                             next_state = WRITE;
                         else 
@@ -120,14 +149,14 @@ always @(posedge HCLK or negedge HRESETn) begin
                 AHB_QSPI_ENABLE <= 1'b0;
             if(qspi_started==1'b1) begin 
                 if(AHB_QSPI_BUSY==1'b0) begin
-                    HRDATA <= AHB_QSPI_RDATA;
+                    HRDATA <= AHB_QSPI_RDATA_i;
                     qspi_ready <= 1'b1;
                 end
             end
         end else begin 
             qspi_started <= 1'b0;
             qspi_ready <=1'b0;
-            AHB_QSPI_ADDR <= HADDR;
+            AHB_QSPI_ADDR <= {HADDR[ADDR_W-1:4],4'b0000};
         end
     end
 

logical/top_ahb_qspi/logical/top_ahb_qspi.v

-
+//-----------------------------------------------------------------------------
+// AHB QSPI Top level
+// A joint work commissioned on behalf of SoC Labs, under Arm Academic Access license.
+//
+// Contributors
+//
+// Daniel Newbrook (d.newbrook@soton.ac.uk)
+// 
+// Copyright � 2021-4, SoC Labs (www.soclabs.org)
+//-----------------------------------------------------------------------------
+// Purpose:
+//   
+//  
+//-----------------------------------------------------------------------------
+// Modules instantiated:
+//  cmsdk_apb_slave_mux (u_cmsdk_apb_slave_mux)
+//  cache_subsystem     (u_cache_subsystem)
+//  qspi_controller_mux (u_qspi_controller_mux)
+//  apb_qspi_regs       (u_apb_qspi_regs)
+//  ahb_qspi_interface  (u_ahb_qspi_interface)
+//  qspi_controller     (u_qspi_controller)
 
 module top_ahb_qspi #(
     parameter ADDR_W = 32,
@@ -128,7 +148,7 @@ cache_subsystem u_cache_subsystem(
     .HSELS(HSELx),
     .HADDRS(HADDR[21:0]),
     .HBURSTS(HBURST),
-    .HMASTLOCKS(1'b1),
+    .HMASTLOCKS(1'b0),
     .HTRANSS(HTRANS),
     .HSIZES(HSIZE),
     .HPROTS(HPROT),

verif/cocotb/makefile

@@ -20,7 +20,7 @@
 
 TOPLEVEL_LANG = verilog
 
-SIM ?= icarus
+SIM ?= questa
 WAVES ?= 0
 GUI ?= 0