Fix paths and remove unwanted files

.gitignore

 simulate/
 
-verif/cocotb/*.ini
-verif/cocotb/*.xml
+verif/cocotb/modelsim.ini
+verif/cocotb/results.xml
 verif/cocotb/transcript
-verif/cocotb/sim_build
-verif/cocotb/__pycache__
+verif/cocotb/ucli.key
+verif/cocotb/ahb_qspi.vcd
+verif/cocotb/transcript
+verif/cocotb/sim_build/
+verif/cocotb/__pycache__/
+
+verif/VIP/sst26wf040b.v

flist/IP/CG092_cache.flist

@@ -2,17 +2,17 @@
 // ============= Verilog library extensions ===========
 +libext+.v+.vlib
 
-+incdir+/Users/danielnewbrook/Documents/SoCLabs/AAA/ip_dir/CG092-BU-50000-r2p0-00rel0/p_flash_cache_f0/logical/p_flash_cache_f0/verilog
++incdir+$(ARM_IP_LIBRARY_PATH)/CG092/CG092-BU-50000-r2p0-00rel0/p_flash_cache_f0/logical/p_flash_cache_f0/verilog
 
-/Users/danielnewbrook/Documents/SoCLabs/AAA/ip_dir/CG092-BU-50000-r2p0-00rel0/p_flash_cache_f0/logical/p_flash_cache_f0/verilog/p_flash_cache_f0_bus_logic.v
-/Users/danielnewbrook/Documents/SoCLabs/AAA/ip_dir/CG092-BU-50000-r2p0-00rel0/p_flash_cache_f0/logical/p_flash_cache_f0/verilog/p_flash_cache_f0_mrb.v
-/Users/danielnewbrook/Documents/SoCLabs/AAA/ip_dir/CG092-BU-50000-r2p0-00rel0/p_flash_cache_f0/logical/p_flash_cache_f0/verilog/p_flash_cache_f0_core.v 
-/Users/danielnewbrook/Documents/SoCLabs/AAA/ip_dir/CG092-BU-50000-r2p0-00rel0/p_flash_cache_f0/logical/p_flash_cache_f0/verilog/p_flash_cache_f0.v
-/Users/danielnewbrook/Documents/SoCLabs/AAA/ip_dir/CG092-BU-50000-r2p0-00rel0/p_flash_cache_f0/logical/p_flash_cache_f0/verilog/p_flash_cache_f0_reg_block.v
+$(ARM_IP_LIBRARY_PATH)/CG092/CG092-BU-50000-r2p0-00rel0/p_flash_cache_f0/logical/p_flash_cache_f0/verilog/p_flash_cache_f0_bus_logic.v
+$(ARM_IP_LIBRARY_PATH)/CG092/CG092-BU-50000-r2p0-00rel0/p_flash_cache_f0/logical/p_flash_cache_f0/verilog/p_flash_cache_f0_mrb.v
+$(ARM_IP_LIBRARY_PATH)/CG092/CG092-BU-50000-r2p0-00rel0/p_flash_cache_f0/logical/p_flash_cache_f0/verilog/p_flash_cache_f0_core.v 
+$(ARM_IP_LIBRARY_PATH)/CG092/CG092-BU-50000-r2p0-00rel0/p_flash_cache_f0/logical/p_flash_cache_f0/verilog/p_flash_cache_f0.v
+$(ARM_IP_LIBRARY_PATH)/CG092/CG092-BU-50000-r2p0-00rel0/p_flash_cache_f0/logical/p_flash_cache_f0/verilog/p_flash_cache_f0_reg_block.v
 
-/Users/danielnewbrook/Documents/SoCLabs/AAA/ip_dir/CG092-BU-50000-r2p0-00rel0/p_flash_cache_f0/logical/models/cells/generic/p_flash_cache_f0_capt_sync.v
-/Users/danielnewbrook/Documents/SoCLabs/AAA/ip_dir/CG092-BU-50000-r2p0-00rel0/p_flash_cache_f0/logical/models/cells/generic/cdc_capt_sync.v
+/$(ARM_IP_LIBRARY_PATH)/CG092/CG092-BU-50000-r2p0-00rel0/p_flash_cache_f0/logical/models/cells/generic/p_flash_cache_f0_capt_sync.v
+/$(ARM_IP_LIBRARY_PATH)/CG092/CG092-BU-50000-r2p0-00rel0/p_flash_cache_f0/logical/models/cells/generic/cdc_capt_sync.v
 
-/Users/danielnewbrook/Documents/SoCLabs/AAA/ip_dir/CG092-BU-50000-r2p0-00rel0/p_flash_cache_f0/logical/models/modules/generic/p_flash_cache_f0_static_reg.v
-/Users/danielnewbrook/Documents/SoCLabs/AAA/ip_dir/CG092-BU-50000-r2p0-00rel0/p_flash_cache_f0/logical/models/modules/generic/static_reg.v
+$(ARM_IP_LIBRARY_PATH)/CG092/CG092-BU-50000-r2p0-00rel0/p_flash_cache_f0/logical/models/modules/generic/p_flash_cache_f0_static_reg.v
+$(ARM_IP_LIBRARY_PATH)/CG092/CG092-BU-50000-r2p0-00rel0/p_flash_cache_f0/logical/models/modules/generic/static_reg.v
 

flist/IP/corstone_101_ip.flist

+$(ARM_IP_LIBRARY_PATH)/latest/Corstone-101/logical/cmsdk_apb_slave_mux/verilog/cmsdk_apb_slave_mux.v
\ No newline at end of file

flist/Top/ahb_QSPI.flist

@@ -7,4 +7,5 @@ $(SOCLABS_AHB_QSPI_DIR)/logical/ahb_qspi_interface/logical/ahb_qspi_interface.sv
 $(SOCLABS_AHB_QSPI_DIR)/logical/qspi_controller/logical/qspi_controller.sv
 
 $(SOCLABS_AHB_QSPI_DIR)/logical/cache_subsytem/logical/cache_subsystem.v
--f $(SOCLABS_AHB_QSPI_DIR)/flist/IP/CG092_cache.flist
+-f $(SOCLABS_AHB_QSPI_DIR)/flist/IP/CG092_cache.flist
\ No newline at end of file
+-f $(SOCLABS_AHB_QSPI_DIR)/flist/IP/corstone_101_ip.flist
\ No newline at end of file

flist/VIP/ahb_QSPI_VIP.flist

-/Users/danielnewbrook/Documents/SoCLabs/AAA/ip_dir/BP210-BU-00000-r1p1-00rel0/logical/cmsdk_ahb_to_apb/verilog/cmsdk_ahb_to_apb.v
+$(ARM_IP_LIBRARY_PATH)/latest/Corstone-101/logical/cmsdk_ahb_to_apb/verilog/cmsdk_ahb_to_apb.v
+
+$(SOCLABS_AHB_QSPI_DIR)/verif/VIP/sst26wf040b.v
\ No newline at end of file

logical/cache_subsytem/logical/cache_subsystem.v

@@ -51,6 +51,34 @@ module cache_subsystem(
     output wire             CACHEHIT
 );
 
+// Data RAM way 0 wires
+wire [7:0]      RAMCLD0ADDR;
+wire            RAMCLD0WE;
+wire [3:0]      RAMCLD0RD;
+wire [3:0]      RAMCLD0CS;
+wire [127:0]    RAMCLD0WDATA;
+wire [127:0]    RAMCLD0RDATA;
+// TAG RAM way 0 wires
+wire [7:0]      RAMTAG0ADDR;
+wire            RAMTAG0WE;
+wire            RAMTAG0RD;
+wire            RAMTAG0CS;
+wire [10:0]     RAMTAG0WDATA;
+wire [10:0]     RAMTAG0RDATA;
+// Data RAM way 1 wires
+wire [7:0]      RAMCLD1ADDR;
+wire            RAMCLD1WE;
+wire [3:0]      RAMCLD1RD;
+wire [3:0]      RAMCLD1CS;
+wire [127:0]    RAMCLD1WDATA;
+wire [127:0]    RAMCLD1RDATA;
+// TAG RAM way 1 wires
+wire [7:0]      RAMTAG1ADDR;
+wire            RAMTAG1WE;
+wire            RAMTAG1RD;
+wire            RAMTAG1CS;
+wire [10:0]     RAMTAG1WDATA;
+wire [10:0]     RAMTAG1RDATA;
 
 
 p_flash_cache_f0 #(
@@ -94,33 +122,33 @@ p_flash_cache_f0 #(
         .RAMPWRUPREQ(),
         .RAMPWRUPACK(),
         // TAG RAM way 0
-        .RAMTAG0ADDR(),
-        .RAMTAG0WE(),
-        .RAMTAG0RD(),
-        .RAMTAG0CS(),
-        .RAMTAG0WDATA(),
-        .RAMTAG0RDATA(),
+        .RAMTAG0ADDR(RAMTAG0ADDR),
+        .RAMTAG0WE(RAMTAG0WE),
+        .RAMTAG0RD(RAMTAG0RD),
+        .RAMTAG0CS(RAMTAG0CS),
+        .RAMTAG0WDATA(RAMTAG0WDATA),
+        .RAMTAG0RDATA(RAMTAG0RDATA),
         // Data RAM way 0
-        .RAMCLD0ADDR(),
-        .RAMCLD0WE(),
-        .RAMCLD0RD(),
-        .RAMCLD0CS(),
-        .RAMCLD0WDATA(),
-        .RAMCLD0RDATA(),
+        .RAMCLD0ADDR(RAMCLD0ADDR),
+        .RAMCLD0WE(RAMCLD0WE),
+        .RAMCLD0RD(RAMCLD0RD),
+        .RAMCLD0CS(RAMCLD0CS),
+        .RAMCLD0WDATA(RAMCLD0WDATA),
+        .RAMCLD0RDATA(RAMCLD0RDATA),
         // TAG RAM way 1
-        .RAMTAG1ADDR(),
-        .RAMTAG1WE(),
-        .RAMTAG1RD(),
-        .RAMTAG1CS(),
-        .RAMTAG1WDATA(),
-        .RAMTAG1RDATA(),
+        .RAMTAG1ADDR(RAMTAG1ADDR),
+        .RAMTAG1WE(RAMTAG1WE),
+        .RAMTAG1RD(RAMTAG1RD),
+        .RAMTAG1CS(RAMTAG1CS),
+        .RAMTAG1WDATA(RAMTAG1WDATA),
+        .RAMTAG1RDATA(RAMTAG1RDATA),
         // Data RAM Way 1
-        .RAMCLD1ADDR(),
-        .RAMCLD1WE(),
-        .RAMCLD1RD(),
-        .RAMCLD1CS(),
-        .RAMCLD1WDATA(),
-        .RAMCLD1RDATA(),
+        .RAMCLD1ADDR(RAMCLD1ADDR),
+        .RAMCLD1WE(RAMCLD1WE),
+        .RAMCLD1RD(RAMCLD1RD),
+        .RAMCLD1CS(RAMCLD1CS),
+        .RAMCLD1WDATA(RAMCLD1WDATA),
+        .RAMCLD1RDATA(RAMCLD1RDATA),
         // AHB Manager
         .HSELM(HSELM),
         .HADDRM(HADDRM),

logical/top_ahb_qspi/logical/top_ahb_qspi.sv

@@ -23,7 +23,7 @@ module top_ahb_qspi #(
     output wire                 HRESP,
 
     // APB Signals
-    input  wire [11:2]          PADDR,
+    input  wire [15:0]          PADDR,
     input  wire [2:0]           PPROT,
     input  wire                 PSEL,
     input  wire                 PENABLE,
@@ -42,23 +42,120 @@ module top_ahb_qspi #(
     output wire [3:0]           QSPI_IO_e
 );
 
+
+wire             qspi_psel;
+wire     [31:0]  qspi_prdata;
+wire             qspi_pready;
+wire             qspi_pslverr;
+
+wire             cache_psel;
+wire     [31:0]  cache_prdata;
+wire             cache_pready;
+wire             cache_pslverr;
+
+
+cmsdk_apb_slave_mux #(
+    .PORT0_ENABLE  (1), // QSPI Control
+    .PORT1_ENABLE  (1), // Cache Control
+    .PORT2_ENABLE  (0), // not used
+    .PORT3_ENABLE  (0), // not used
+    .PORT4_ENABLE  (0), // not used
+    .PORT5_ENABLE  (0), // not used
+    .PORT6_ENABLE  (0), // not used
+    .PORT7_ENABLE  (0), // not used
+    .PORT8_ENABLE  (0), // not used
+    .PORT9_ENABLE  (0), // not used
+    .PORT10_ENABLE (0), // not used
+    .PORT11_ENABLE (0), // not used
+    .PORT12_ENABLE (0),
+    .PORT13_ENABLE (0),
+    .PORT14_ENABLE (0),
+    .PORT15_ENABLE (0)
+) u_cmsdk_apb_slave_mux (
+    // Inputs
+    .DECODE4BIT        (PADDR[15:12]),
+    .PSEL              (PSEL),
+    // PSEL (output) and return status & data (inputs) for each port
+    .PSEL0             (qspi_psel),
+    .PREADY0           (qspi_pready),
+    .PRDATA0           (qspi_prdata),
+    .PSLVERR0          (qspi_pslverr),
+
+    .PSEL1             (cache_psel),
+    .PREADY1           (cache_pready),
+    .PRDATA1           (cache_prdata),
+    .PSLVERR1          (cache_pslverr),
+
+    // Output
+    .PREADY            (PREADY),
+    .PRDATA            (PRDATA),
+    .PSLVERR           (PSLVERR)
+
+);
+
 cache_subsystem u_cache_subsystem(
+    .HCLK(HCLK),
+    .HRESETn(HRESETn),
+
+    .PCLKG(PCLK),
+    .PADDR(PADDR[11:0]),
+    .PWDATA(PWDATA),
+    .PWRITE(PWRITE),
+    .PSEL(cache_psel),
+    .PENABLE(PENABLE),
+    .PSTRB(PSTRB),
+    .PPROT(PPROT),
+    .PRDATA(cache_prdata),
+    .PSLVERR(cache_pslverr),
+    .PREADY(cache_pready),
+
+    .HSELS(),
+    .HADDRS(),
+    .HBURSTS(),
+    .HMASTLOCKS(),
+    .HTRANSS(),
+    .HSIZES(),
+    .HPROTS(),
+    .HWRITES(),
+    .HWDATAS(),
+    .HREADYS(),
+    .HMASTERS(),
+    .HREADYOUTS(),
+    .HRDATAS(),
+    .HRESPS(),
+
+    .HSELM(),
+    .HADDRM(),
+    .HBURSTM(),
+    .HMASTLOCKM(),
+    .HTRANSM(),
+    .HSIZEM(),
+    .HPROTM(),
+    .HWRITEM(),
+    .HWDATAM(),
+    .HREADYM(),
+    .HREADYOUTM(),
+    .HRDATAM(),
+    .HRESPM(),
 
+    .IRQ(),
+    .CACHEMISS(),
+    .CACHEHIT()
 );
 
 apb_qspi_regs u_apb_qspi_regs(
     .PCLK(PCLK),
     .PRESETn(PRESETn),
-    .PADDR(PADDR),
+    .PADDR(PADDR[11:2]),
     .PPROT(PPROT),
-    .PSEL(PSEL),
+    .PSEL(qspi_psel),
     .PENABLE(PENABLE),
     .PWRITE(PWRITE),
     .PWDATA(PWDATA),
     .PSTRB(PSTRB),
-    .PRDATA(PRDATA),
-    .PREADY(PREADY),
-    .PSLVERR(PSLVERR)
+    .PRDATA(qspi_prdata),
+    .PREADY(qspi_pready),
+    .PSLVERR(qspi_pslverr)
 );
 
 ahb_qspi_interface #(

makefile

@@ -20,6 +20,9 @@ else
 	DESIGN_VC ?= $(SOCLABS_AHB_QSPI_DIR)/flist/Top/ahb_QSPI_SIM.flist
 endif
 
+get_flash_model:
+	@cd $(SOCLABS_AHB_QSPI_DIR)/verif/VIP; wget https://ww1.microchip.com/downloads/en/DeviceDoc/sst26wf040b.v
+
 #Include flows
 include ./flows/makefile.simulate
 

verif/cocotb/ahb_qspi_cocotb.v

@@ -39,7 +39,7 @@ begin
 end
 
 
-wire [11:0]          PADDR;
+wire [15:0]          PADDR;
 wire [2:0]           PPROT;
 wire                 PSEL;
 wire                 PENABLE;
@@ -51,7 +51,7 @@ wire                 PREADY;
 wire                 PSLVERR;   
 
 cmsdk_ahb_to_apb #(
-    .ADDRWIDTH(12),
+    .ADDRWIDTH(16),
     .REGISTER_RDATA(1),
     .REGISTER_WDATA(0)
 ) u_cmsdk_ahb_to_apb (
@@ -60,7 +60,7 @@ cmsdk_ahb_to_apb #(
     .PCLKEN(1'b1),
 
     .HSEL(config_HSEL),
-    .HADDR(config_HADDR[11:0]),
+    .HADDR(config_HADDR[15:0]),
     .HTRANS(config_HTRANS),
     .HSIZE(config_HSIZE),
     .HPROT(config_HPROT),
@@ -85,6 +85,13 @@ cmsdk_ahb_to_apb #(
     .PSLVERR(PSLVERR)
 );
 
+
+wire QSPI_SCLK;
+wire QSPI_nCS;
+wire [3:0] QSPI_IO_o;
+wire [3:0] QSPI_IO_i;
+wire [3:0] QSPI_IO_e;
+wire [3:0] QSPI_IO;
 top_ahb_qspi u_top_ahb_qspi(
     .HCLK(HCLK),
     .HRESETn(HRESETn),
@@ -104,7 +111,7 @@ top_ahb_qspi u_top_ahb_qspi(
     .HREADYOUT(data_HREADY),
     .HRESP(data_HRESP),
     
-    .PADDR(PADDR[11:2]),
+    .PADDR(PADDR),
     .PPROT(PPROT),
     .PSEL(PSEL),
     .PENABLE(PENABLE),
@@ -114,14 +121,35 @@ top_ahb_qspi u_top_ahb_qspi(
     .PRDATA(PRDATA),
     .PREADY(PREADY),
     .PSLVERR(PSLVERR), 
-    .QSPI_SCLK(),
-    .QSPI_nCS(),
-    .QSPI_IO_o(),
-    .QSPI_IO_i(),
-    .QSPI_IO_e()
+    .QSPI_SCLK(QSPI_SCLK),
+    .QSPI_nCS(QSPI_nCS),
+    .QSPI_IO_o(QSPI_IO_o),
+    .QSPI_IO_i(QSPI_IO_i),
+    .QSPI_IO_e(QSPI_IO_e)
 );
 
+assign QSPI_IO[0] = QSPI_IO_e[0] ? QSPI_IO_o[0] : 1'bz;
+assign QSPI_IO[1] = QSPI_IO_e[1] ? QSPI_IO_o[1] : 1'bz;
+assign QSPI_IO[2] = QSPI_IO_e[2] ? QSPI_IO_o[2] : 1'bz;
+assign QSPI_IO[3] = QSPI_IO_e[3] ? QSPI_IO_o[3] : 1'bz;
 
+assign QSPI_IO_i[0] = QSPI_IO[0];
+assign QSPI_IO_i[1] = QSPI_IO[1];
+assign QSPI_IO_i[2] = QSPI_IO[2];
+assign QSPI_IO_i[3] = QSPI_IO[3];
+
+sst26wfxxxb u_sst26wfxxxb(
+    .SCK(QSPI_SCLK),
+    .SIO(QSPI_IO),
+    .CEb(QSPI_nCS)
+);
 
+defparam u_sst26wfxxxb.Ksize = 4096;
+defparam u_sst26wfxxxb.Msize = 4;
+defparam u_sst26wfxxxb.ADDR_MSB = 21;
+defparam u_sst26wfxxxb.Memory_Capacity = 8'h52;
+defparam u_sst26wfxxxb.WLLD_value = 24'h00_0000;
+defparam u_sst26wfxxxb.INIT_WPEN = 1'b0;
+defparam u_sst26wfxxxb.SECURITY_LOCKOUT_VALUE = 1'b0;
 
 endmodule 
\ No newline at end of file

verif/cocotb/ahb_qspi_tests.py

@@ -13,8 +13,8 @@ from cocotbext.ahb import AHBLiteMaster, AHBBus
 
 FREQ = 240
 
-CONFIG_ADDR = 0x0
-DATA_ADDR = 0x10000000
+QSPI_CONFIG_ADDR = 0x0
+CACHE_CONFIG_ADDR = 0x1000
 
 class TB:
     def __init__(self,dut):
@@ -47,3 +47,13 @@ async def AHB_QSPI_1(dut):
     print(data)
     data = await tb.config_ahb_master.read(0x04,4)
     assert int(data[0]['data'],16) == 0xcafecafe
+
+@cocotb.test()
+async def CACHE_CONFIG(dut):
+    tb = TB(dut)
+    await tb.cycle_reset()
+    data = await tb.config_ahb_master.read(CACHE_CONFIG_ADDR,4)
+    # After reset CCR register should = 0x40
+    assert int(data[0]['data'],16) == 0x40
+    data = await tb.config_ahb_master.read(CACHE_CONFIG_ADDR+0x20,4)
+    print(data)
\ No newline at end of file

verif/cocotb/makefile

@@ -31,7 +31,7 @@ DUT      = ahb_qspi_cocotb
 TOPLEVEL = ahb_qspi_cocotb
 MODULE   = ahb_qspi_tests
 
-VERILOG_SOURCES += ./ahb_qspi_cocotb.v
+VERILOG_SOURCES += $(SOCLABS_AHB_QSPI_DIR)/verif/cocotb/ahb_qspi_cocotb.v
 
 ifeq ($(SIM), icarus)
 	PLUSARGS += -fst

verif/cocotb/results.xml

-<testsuites name="results">
-  <testsuite name="all" package="all">
-    <property name="random_seed" value="1726223252" />
-    <testcase classname="ahb_qspi_tests" file="/home/dwn1c21/SoC-Labs/ahb_qspi/verif/cocotb/ahb_qspi_tests.py" lineno="29" name="AHB_QSPI_1" ratio_time="57536.30253728772" sim_time_ns="1290.001" time="0.022420644760131836">
-      <failure message="Test failed with RANDOM_SEED=1726223252" />
-    </testcase>
-  </testsuite>
-</testsuites>

verif/cocotb/sim_build/runsim.do

-# Autogenerated file
-onerror {
-	quit -f -code 1
-}
-vmap -c
-if [file exists sim_build/work] {vdel -lib sim_build/work -all}
-vlib sim_build/work
-vmap work sim_build/work
-vlog -work work +define+COCOTB_SIM -sv -timescale 1ns/1ns -mfcu +acc +acc  ./ahb_qspi_cocotb.v
-vsim  -onfinish exit -pli /usr/local/lib64/python3.6/site-packages/cocotb/libs/libcocotbvpi_modelsim.so   sim_build/work.ahb_qspi_cocotb
-onbreak resume
-run -all
-quit