DM230 default to allow AES128 project to work

flist/project/accelerator.flist

@@ -14,10 +14,10 @@
 // =============    Accelerator Module search path    =============
 
 // ! Point this to your Accelerator RTL
-//+incdir+$(ACCELERATOR_DIR)/src/rtl
++incdir+$(ACCELERATOR_DIR)/src/rtl
 
 // ! Point this to your Wrapper RTL
-///$(SOCLABS_PROJECT_DIR)/wrapper/src/soclabs_ahb_aes128_ctrl.v
+$(SOCLABS_PROJECT_DIR)/wrapper/src/soclabs_ahb_aes128_ctrl.v
 
 // ! Point this to your Subsystem RTL
-///$(SOCLABS_PROJECT_DIR)/system/src/accelerator_subsystem.v
+$(SOCLABS_PROJECT_DIR)/system/src/accelerator_subsystem.v

flist/project/system.flist

@@ -32,4 +32,8 @@
 -f $(SOCLABS_WRAPPER_TECH_DIR)/flist/accelerator_wrapper_ip.flist
 
 // - Bootrom Code RTL
-$(SOCLABS_PROJECT_DIR)/system/src/bootrom/verilog/bootrom.v
+$(SOCLABS_PROJECT_DIR)/system/src/bootrom/verilog/bootrom.v
\ No newline at end of file
+
+// the chosen DMA controller
+//-f $(SOCLABS_SLDMA350_TECH_DIR)/flist/sldma350_ahb.flist
+-f $(SOCLABS_SLDMA230_TECH_DIR)/flist/sldma230_ip.flist

nanosoc_tech @ 5a0f5c8b

-Subproject commit 872cd269323ed2cf442aff3830cb46ab25846ad8
+Subproject commit 5a0f5c8b88fc323c52701c75f7665bf948d7b16a