quickstart branch added and README updated

README.md

@@ -28,6 +28,15 @@ The /env/dependency_env.sh file is already modified to include the accelerator d
 
 `export ACCELERATOR_DIR="$SOCLABS_PROJECT_DIR/secworks-aes"`
 
+## QUICKSTART branch
+--
+
+A "quickstart" branch has been added which uses the Quick-Start Arm Cortex-M0 CPU but no DMA controller is available without full Arm-Academic-Access license IP bundles. The branch simply modifies the `nanosoc.config` file - and adds this paragraph to the README.
+For simulation and fpga building `QUICKSTART=yes` must be added to the make target arguments.
+The software-only verification (`TESTNAME=aes128_tests_memcpy`) passes but the hardware DMA test exits with `TEST SKIPPED` message as the DMA controller accesses fault (`TESTNAME=aes128_tests_dma230`)
+To generate the html documentation use:
+
+`htmlgen -f $SOCLABS_PROJECT_DIR/flist/project/top_qs.flist`
 
 ### Setting up the Project Environment
 ---

nanosoc.config

@@ -8,10 +8,10 @@
 #### IP Configuration 
 # !!EDIT this to point to the relevant logical directories of IP
 ARM_CORSTONE_101_DIR ?= $(ARM_IP_LIBRARY_PATH)/latest/Corstone-101/logical
-ARM_CORTEX_M0_DIR    ?= $(ARM_IP_LIBRARY_PATH)/latest/Cortex-M0/logical
+ARM_CORTEX_M0_DIR    ?= $(ARM_IP_LIBRARY_PATH)/latest/Cortex-M0-QS/Cortex-M0-logical
 
 # DMA_xxx_INCLUDE (yes or leave blank)
-DMA_0_PL230_INCLUDE := yes 
+DMA_0_PL230_INCLUDE := 
 DMA_1_PL230_INCLUDE := 
 DMA_DMA350_INCLUDE := 
 
@@ -37,4 +37,4 @@ SNPS_PVT_TS_3_INCLUDE:=
 SNPS_PVT_TS_4_INCLUDE:=
 SNPS_PVT_TS_5_INCLUDE:=
 SNPS_PVT_PD_0_INCLUDE:=
-SNPS_PVT_VM_0_INCLUDE:=
\ No newline at end of file
+SNPS_PVT_VM_0_INCLUDE:=