accelerator_subsystem.v

//-----------------------------------------------------------------------------
// SoC Labs Accelerator Subsystem for SecWorks AES-128 Accelerator
// A joint work commissioned on behalf of SoC Labs; under Arm Academic Access license.
//
// Contributors
//
// David Mapstone (d.a.mapstone@soton.ac.uk)
// David Flynn    (d.w.flynn@soton.ac.uk)
//
// Copyright (C) 2023; SoC Labs (www.soclabs.org)
//-----------------------------------------------------------------------------
`include "gen_defines.v"

module accelerator_subsystem #(
  parameter SYS_ADDR_W = 32,
  parameter SYS_DATA_W = 32,
  parameter ACC_ADDR_W = 16,
  parameter IRQ_NUM    = 4
) (
  input  wire                      HCLK,       // Clock
  input  wire                      HRESETn,    // Reset

  // AHB connection to Initiator
  input  wire                      HSEL,
  input  wire   [SYS_ADDR_W-1:0]   HADDR,
  input  wire   [1:0]              HTRANS,
  input  wire   [2:0]              HSIZE,
  input  wire   [3:0]              HPROT,
  input  wire                      HWRITE,
  input  wire                      HREADY,
  input  wire   [SYS_DATA_W-1:0]   HWDATA,

  output wire                      HREADYOUT,
  output wire                      HRESP,
  output wire   [SYS_DATA_W-1:0]   HRDATA,

  // Data Request Signal to DMAC
  output wire   [1:0]              EXP_DRQ,
  input  wire   [1:0]              EXP_DLAST,
   // DMAC Stream interfaces
`ifdef DMAC_1_DMA350
  input  wire                      EXP_STR_IN_0_TVALID,
  output wire                      EXP_STR_IN_0_TREADY,
  input  wire [SYS_DATA_W-1:0]     EXP_STR_IN_0_TDATA,
  input  wire [15:0]               EXP_STR_IN_0_TSTRB,
  input  wire                      EXP_STR_IN_0_TLAST,

  output wire                      EXP_STR_OUT_0_TVALID,
  input  wire                      EXP_STR_OUT_0_TREADY,
  output wire [SYS_DATA_W-1:0]     EXP_STR_OUT_0_TDATA,
  output wire [15:0]               EXP_STR_OUT_0_TSTRB,
  output wire                      EXP_STR_OUT_0_TLAST,
  input  wire                      EXP_STR_OUT_0_FLUSH,

  input  wire                      EXP_STR_IN_1_TVALID,
  output wire                      EXP_STR_IN_1_TREADY,
  input  wire [SYS_DATA_W-1:0]     EXP_STR_IN_1_TDATA,
  input  wire [15:0]               EXP_STR_IN_1_TSTRB,
  input  wire                      EXP_STR_IN_1_TLAST,

  output wire                      EXP_STR_OUT_1_TVALID,
  input  wire                      EXP_STR_OUT_1_TREADY,
  output wire [SYS_DATA_W-1:0]     EXP_STR_OUT_1_TDATA,
  output wire [15:0]               EXP_STR_OUT_1_TSTRB,
  output wire                      EXP_STR_OUT_1_TLAST,
  input  wire                      EXP_STR_OUT_1_FLUSH,
`endif 

  // Interrupts
  output wire   [IRQ_NUM-1:0]      EXP_IRQ
);
  
  //-------------------------------------------
  // Instantiate your accelerator/wrapper here
  //-------------------------------------------
  

endmodule