SOC1-127: Added additional interfaces to wrapper packet deconstruct

hdl/src/wrapper_packet_deconstruct.sv

@@ -16,21 +16,36 @@ module  wrapper_packet_deconstruct #(
   input  logic                  hclk,       // clock
   input  logic                  hresetn,    // reset
 
-   //Register interface
-  input  logic [ADDRWIDTH-1:0]   addr,
-  input  logic                   read_en,
-  input  logic                   write_en,
-  input  logic [3:0]             byte_strobe,
-  input  logic [31:0]            wdata,
-  output logic [31:0]            rdata,
-  output logic                   wready,
-  output logic                   rready,
+  // AHB Register interface
+  input  logic [ADDRWIDTH-1:0]   ahb_addr,
+  input  logic                   ahb_read_en,
+  input  logic                   ahb_write_en,
+  input  logic [3:0]             ahb_byte_strobe,
+  input  logic [31:0]            ahb_wdata,
+  output logic [31:0]            ahb_rdata,
+  output logic                   ahb_wready,
+  output logic                   ahb_rready,
+
+  // APB Register Interface (IRQ Registers)
+  input  logic [ADDRWIDTH-1:0]   apb_addr,
+  input  logic                   apb_read_en,
+  input  logic                   apb_write_en,
+  input  logic [3:0]             apb_byte_strobe,
+  input  logic [31:0]            apb_wdata,
+  output logic [31:0]            apb_rdata,
+  output logic                   apb_wready,
+  output logic                   apb_rready,
 
   // Valid/Ready interface
   input  logic [PACKETWIDTH-1:0] packet_data,
   input  logic                   packet_data_last,
   input  logic                   packet_data_valid,
-  output logic                   packet_data_ready
+  output logic                   packet_data_ready,
+  input  logic                   packet_count,
+
+  // IRQ Control
+  input  logic                   irq_ack,
+  output logic                   irq_out
 );
 
 // Create Deconstruction Buffer
@@ -42,12 +57,14 @@ logic [(PACKETWIDTH/32)-1:0] deconst_buf_flag;
 
 // Select which word in buffer to read 
 logic [$clog2(PACKETWIDTH/32)-1:0] buf_word_sel;
-assign buf_word_sel = addr[($clog2(PACKETWIDTH/32)-1)+2:2];
+assign buf_word_sel = ahb_addr[($clog2(PACKETWIDTH/32)-1)+2:2];
 
 // Curent Buffer Flag
 logic [(PACKETWIDTH/32)-1:0] cur_deconst_buf_flag;
 assign cur_deconst_buf_flag = 1'b1 << buf_word_sel;
 
+// Register to Hold Last Flag
+logic deconst_buf_last;
 // Check All Flags are High
 logic deconst_buf_flag_reduced;
 assign deconst_buf_flag_reduced = &(deconst_buf_flag | (cur_deconst_buf_flag));
@@ -60,13 +77,14 @@ logic deconst_buf_valid;
 always_ff @(posedge hclk or negedge hresetn) begin
     if (~hresetn) begin
         // Reset Construction Buffer
-        deconst_buf   <= {PACKETWIDTH{1'b0}};
+        deconst_buf          <= {PACKETWIDTH{1'b0}};
         // Reset Values
-        packet_data_ready  <= 1'b0;
-        deconst_buf_valid  <= 1'b0;
-        deconst_buf_flag   <= {(PACKETWIDTH/32){1'b0}};
+        packet_data_ready    <= 1'b0;
+        deconst_buf_valid    <= 1'b0;
+        deconst_buf_flag     <= {(PACKETWIDTH/32){1'b0}};
+        deconst_buf_last     <= 1'b1;
     end else begin
-        // If ready is low and theres no valid data in buffer, asser ready
+        // If ready is low and theres no valid data in buffer, assert ready
         if (!packet_data_ready && !deconst_buf_valid) begin
             packet_data_ready  <= 1'b1;
         end
@@ -75,9 +93,19 @@ always_ff @(posedge hclk or negedge hresetn) begin
             packet_data_ready  <= 1'b0;
             deconst_buf        <= packet_data;
             deconst_buf_valid  <= 1'b1;
+            deconst_buf_last   <= packet_data_last;
             deconst_buf_flag   <= {(PACKETWIDTH/32){1'b0}};
+
+            // If First Packet of Block
+            if (deconst_buf_last) begin
+                // Read in Number of Packets
+
+                // Calculate Start Address
+
+                // Write Start Address to Register
+            end
         end
-        if (read_en) begin
+        if (ahb_read_en) begin
             // Register which words in the Deconstruction buffer have been read
             // Check if All Words have been Read
             if (deconst_buf_flag_reduced && !(packet_data_valid && packet_data_ready)) begin
@@ -93,20 +121,20 @@ end
 
 // Read Condition
 always_comb begin
-    if (read_en) begin
+    if (ahb_read_en) begin
         // Read appropriate 32 bits from buffer - wrapping behaviour
-        rdata = deconst_buf[buf_word_sel];
+        ahb_rdata = deconst_buf[buf_word_sel];
     end else begin
-        rdata = 32'd0;
+        ahb_rdata = 32'd0;
     end
 end
 
 // Register Ready Control
 always_comb begin
     // Not Ready Out when waiting for Valid Data on Input
-    rready = ~packet_data_ready;
+    ahb_rready = ~packet_data_ready;
     // Write Ready always high but doesn't do anywthing
-    wready = 1'b1;
+    ahb_wready = 1'b1;
 end
 
 endmodule
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