Successfull Simulation of AHB to VR to AHB

flow/stimgen.py

 import csv, os, tabulate
+from enum import Enum
 
 soclabs_header = """;#-----------------------------------------------------------------------------
 ;# SoC Labs Basic Hashing Accelerator Wrapper Input Stimulus File
@@ -11,6 +12,28 @@ soclabs_header = """;#----------------------------------------------------------
 ;# Copyright  2023, SoC Labs (www.soclabs.org)
 ;#-----------------------------------------------------------------------------"""
 
+class TransactionType(Enum):
+    """ Enumerated Types for Transaction Types for ASCII Debug """
+    READ  = 1
+    WRITE = 2
+    def __str__(self):
+        match self:
+            case TransactionType.READ:
+                return "R"
+            case TransactionType.WRITE:
+                return "W"
+
+class TransactionSize(Enum):
+    """ Enumerated Types for Transaction Types for ASCII Debug """
+    WORD     = 1
+    HALFWORD = 2
+    def __str__(self):
+        match self:
+            case TransactionSize.WORD:
+                return "word"
+            case TransactionSize.HALFWORD:
+                return "halfword"
+
 class InputBlockStruct:
     def __init__(self):
         self.word_list = []
@@ -26,7 +49,7 @@ class InputPacketStruct:
         self.block_list.append(block)
 
 class WordStruct:
-    def __init__(self, data = 0x0, addr = 0x0, packet_num = 0, block_num = 0, trans = "W", size ="word" ):
+    def __init__(self, data, addr, trans, packet_num = 0, block_num = 0, size = TransactionSize.WORD):
         self.data = data
         self.addr = addr
         self.trans = trans
@@ -106,11 +129,17 @@ def stimulus_generation(in_file, start_address, size):
         # print(f"Packet: {int(packet_num)} | Start Address: {hex(start_write_addr)}")
         write_addr = start_write_addr
         for block_num, block in enumerate(packet.block_list):
+            read_address = write_addr + 0x0000_0800
             for word in block.word_list:
-                word_data = WordStruct(word, write_addr, packet_num, block_num)
+                word_data = WordStruct(word, write_addr, TransactionType.WRITE, packet_num, block_num)
                 output_word_list.append(word_data)
                 # Increment Address
                 write_addr += 0x4
+            for word in block.word_list:
+                word_data = WordStruct(word, read_address, TransactionType.READ, packet_num, block_num)
+                output_word_list.append(word_data)
+                # Increment Address
+                read_address += 0x4
 
     # Generate FRI File with Write Transactions
     fri_file = os.environ["WRAP_ACC_DIR"] + "/simulate/stimulus/" + "ahb_input_hash_stim.fri"

hdl/src/wrapper_packet_construct.sv

@@ -57,6 +57,10 @@ always_ff @(posedge hclk or negedge hresetn) begin
         data_out       <= {PACKETWIDTH{1'b0}};
         last_wr_addr   <= {ADDRWIDTH{1'b0}};
     end else begin
+        // Handshake Output
+        if (data_out_ready && data_out_valid) begin
+            data_out_valid <= 1'b0;
+        end
         if (write_en) begin
             // If not (awaiting handshake AND address generates new data payload)
             if (!((data_out_valid && !data_out_ready) && (addr[5:2] == 4'hF))) begin

hdl/src/wrapper_packet_deconstruct.sv

@@ -50,7 +50,7 @@ assign deconst_buf_flag_reduced = &(deconst_buf_flag | (cur_deconst_buf_flag));
 
 // Select which word in buffer to read 
 logic [$clog2(PACKETWIDTH/32)-1:0] buf_word_sel;
-assign buf_word_sel = addr[4:2];
+assign buf_word_sel = addr[($clog2(PACKETWIDTH/32)-1)+2:2];
 
 logic deconst_buf_valid;
 // Dump data on one of two conditions

hdl/verif/tb_wrapper_top.sv

@@ -52,7 +52,7 @@ parameter ADDRWIDTH = 12;
 // parameter InputFileName = "ahb_input_hash_stim.m2d";
 parameter InputFileName = ("../stimulus/ahb_input_hash_stim.m2d");
 parameter MessageTag = "FileReader:";
-parameter StimArraySize = 5000;
+parameter StimArraySize = 10000;
 
 
 //********************************************************************************