SOC1-141: Added data request module to ahb packet constructor module

flist/wrapper_ip.flist

@@ -19,6 +19,9 @@
 -y $(ACC_WRAPPER_DIR)/hdl/src/
 +incdir+$(ACC_WRAPPER_DIR)/hdl/src/
 
+$(ACC_WRAPPER_DIR)/hdl/src/wrapper_ahb_packet_constructor.sv
+
+$(ACC_WRAPPER_DIR)/hdl/src/wrapper_data_req.sv
 $(ACC_WRAPPER_DIR)/hdl/src/wrapper_ahb_reg_interface.sv
 $(ACC_WRAPPER_DIR)/hdl/src/wrapper_ahb_vr_interface.sv
 $(ACC_WRAPPER_DIR)/hdl/src/wrapper_packet_construct.sv

hdl/src/wrapper_ahb_packet_constructor.sv

@@ -8,7 +8,7 @@
 //
 // Copyright  2023, SoC Labs (www.soclabs.org)
 //-----------------------------------------------------------------------------
-module wrapper_ahb_interface #(
+module wrapper_ahb_packet_constructor #(
   //parameter for address width
   parameter   ADDRWIDTH=11,
   parameter   PACKETWIDTH=512
@@ -33,7 +33,10 @@ module wrapper_ahb_interface #(
   output logic [PACKETWIDTH-1:0] packet_data,
   output logic                   packet_data_last,
   output logic                   packet_data_valid,
-  input  logic                   packet_data_ready
+  input  logic                   packet_data_ready,
+
+  // Data Request Signal
+  output logic                   data_req
  );
 
  // Register Interface Connections
@@ -46,6 +49,9 @@ module wrapper_ahb_interface #(
  logic                  wready;
  logic                  rready;
 
+ // Engine Ready for more Data
+ logic engine_ready;
+
  // AHB Interface Instantiation
  wrapper_ahb_reg_interface #(
     ADDRWIDTH
@@ -77,6 +83,28 @@ module wrapper_ahb_interface #(
     .rready      (rready)
  );
 
+ // Data Request Signal Generator
+ wrapper_data_req #(
+    ADDRWIDTH,  // Only half address map allocated to this device
+    512         // Packet Width
+  ) u_wrapper_data_req (
+    .hclk           (hclk),
+    .hresetn        (hresetn),
+
+    // AHB Address Phase Signaling
+    .hsels          (hsels),
+    .haddrs         (haddrs),
+    .htranss        (htranss),
+    .hreadys        (hreadys),
+
+    // Engine Data Ready Signal
+    .engine_ready   (engine_ready),
+
+    // Data Request Signal 
+    .data_req       (data_req)
+ );
+ 
+ // Valid/Ready Packet Generator
  wrapper_packet_construct #(
     ADDRWIDTH,  // Only half address map allocated to this device
     512         // Packet Width
@@ -98,6 +126,9 @@ module wrapper_ahb_interface #(
     .packet_data       (packet_data),
     .packet_data_last  (packet_data_last),
     .packet_data_valid (packet_data_valid),
-    .packet_data_ready (packet_data_ready)
+    .packet_data_ready (packet_data_ready),
+
+    // Data Request 
+    .engine_ready      (engine_ready)
   );
 endmodule
\ No newline at end of file

hdl/src/wrapper_ahb_reg_interface.sv

@@ -67,12 +67,13 @@ module wrapper_ahb_reg_interface #(
 
   // ----------------------------------------
   // Internal logics declarations
-   logic                   trans_req= hreadys & hsels & htranss[1];
+   logic                   trans_req;
+   assign                  trans_req = hreadys & hsels & htranss[1];
     // transfer request issued only in SEQ and NONSEQ status and slave is
     // selected and last transfer finish
 
-   logic                   ahb_read_req  = trans_req & (~hwrites);// AHB read request
-   logic                   ahb_write_req = trans_req &  hwrites;  // AHB write request
+   logic                   ahb_read_req;// AHB read request
+   logic                   ahb_write_req;  // AHB write request
    logic                   update_read_req;    // To update the read enable register
    logic                   update_write_req;   // To update the write enable register
 
@@ -86,6 +87,9 @@ module wrapper_ahb_reg_interface #(
    logic  [1:0]             haddrs_byte_sel; // Select which byte to enable
    logic                    haddrs_halfword_sel; // Select which byte to enable
 
+   assign                  ahb_read_req  = trans_req & (~hwrites);
+   assign                  ahb_write_req = trans_req &  hwrites; 
+   
    assign haddrs_byte_sel     = haddrs[1:0];
    assign haddrs_halfword_sel = haddrs[1];
   //-----------------------------------------------------------

hdl/src/wrapper_data_req.sv

+//-----------------------------------------------------------------------------
+// SoC Labs AHB Wrapper Write Ready Generator
+// - Adapted from ARM AHB-lite example slave interface module.
+// A joint work commissioned on behalf of SoC Labs, under Arm Academic Access license.
+//
+// Contributors
+//
+// David Mapstone (d.a.mapstone@soton.ac.uk)
+//
+// Copyright  2023, SoC Labs (www.soclabs.org)
+//-----------------------------------------------------------------------------
+//-----------------------------------------------------------------------------
+// Abstract : Looks for last word address of packet during address phase 
+//            to de-assert accelerator ready signal.
+//-----------------------------------------------------------------------------
+module wrapper_data_req #(
+  parameter   ADDRWIDTH=11,
+  parameter   PACKETWIDTH=512
+)(
+  input  logic                  hclk,       // clock
+  input  logic                  hresetn,    // reset
+
+  // AHB connection to master (Address-phase signals only)
+  input  logic                  hsels,
+  input  logic [ADDRWIDTH-1:0]  haddrs,
+  input  logic [1:0]            htranss,
+  input  logic                  hreadys,
+
+  // Engine Hungry Signal
+  input  logic                  engine_ready,
+
+  // Connection to wrapper
+  output logic                  data_req
+);
+
+localparam REGDWIDTH       = 32; // Register Data Width
+localparam PACKETBYTEWIDTH = $clog2(PACKETWIDTH/8); // Number of Bytes in Packet
+localparam REGDBYTEWIDTH   = $clog2(REGDWIDTH/8); // Number of Bytes in Register Data Word
+
+logic trans_req;
+assign trans_req  = hreadys & hsels & htranss[1];
+
+// Check if current address is last word in packet
+logic packet_last_word;
+assign packet_last_word = &haddrs[PACKETBYTEWIDTH-1:REGDBYTEWIDTH];
+
+// If engine_ready => data_req EXCEPT if current address is last address
+logic engine_ready_reg;
+logic data_req_latched;
+
+always_ff @(posedge hclk or negedge hresetn) begin
+    if (~hresetn) begin
+        engine_ready_reg <= 1'b0;
+        data_req_latched <= 1'b0;
+    end else begin
+        // Buffer engine ready signal to determine state change
+        engine_ready_reg <= engine_ready;
+        // Latch data request signal once seen last address of packet
+        if (trans_req && packet_last_word && engine_ready) begin
+            // Latch data request signal
+            data_req_latched <= 1'b1;
+        // Unlatch when latched and data phase finished
+        end else if (data_req_latched && hreadys) begin
+            // Unlatch data request signal
+            data_req_latched <= 1'b0;
+        end
+    end
+end
+
+always_comb begin
+    if (~engine_ready_reg) begin
+        // If engine ready is transitioning from low to high
+        data_req = engine_ready;
+    end else begin
+        // If seeing last word of packet address and valid transfer request
+        if ((trans_req && packet_last_word) || data_req_latched) begin
+            // Drop data request signal after address phase of last word in packet
+            data_req = 1'b0;
+        end else begin
+            // After data phase, take value of engine ready
+            data_req = engine_ready;
+        end
+    end
+end
+endmodule
\ No newline at end of file

hdl/src/wrapper_packet_construct.sv

@@ -30,7 +30,10 @@ module  wrapper_packet_construct #(
   output logic [PACKETWIDTH-1:0] packet_data,
   output logic                   packet_data_last,
   output logic                   packet_data_valid,
-  input  logic                   packet_data_ready
+  input  logic                   packet_data_ready,
+
+  // Data Input Request
+  output logic                   engine_ready
 );
 
 localparam REGDWIDTH       = 32; // Register Data Width
@@ -71,6 +74,9 @@ logic packet_addr_last, prev_packet_addr_last;
 assign packet_addr_last      = &packet_addr;
 assign prev_packet_addr_last = &prev_packet_addr;
 
+// Engine Ready Assignment
+assign engine_ready = packet_data_ready;
+
 // Write data out when either:
 // - Word is last address of current packet
 // - Address Moved to address of different packet