Fixed Address Mapping and fixed construction buffer top address bit value

flow/stimgen.py

@@ -122,6 +122,6 @@ def stimulus_generation(in_file, start_address, size):
 
 if __name__ == "__main__":
     accelerator_input_address = 0x6001_0000
-    accelerator_input_size = 0x0000_8000
+    accelerator_input_size = 0x0000_0800
     in_file = os.environ["SHA_2_ACC_DIR"] + "/simulate/stimulus/system/" + "input_data_32bit_stim.csv"
     stimulus_generation(in_file, accelerator_input_address, accelerator_input_size)
\ No newline at end of file

hdl/src/wrapper_ahb_deconstruct.sv

@@ -30,7 +30,7 @@ logic [PACKETWIDTH-1:0] const_buffer;
 logic const_buffer_last;
 
 logic [ADDRWIDTH-1:0] addr_top_bit;
-assign addr_top_bit = (addr[5:2] * 32) - 1;
+assign addr_top_bit = (addr[5:2] * 32) - 1 + 32;
 
 // Dump data on one of two conditions
 // - An address ends [5:0] in 0x3C i.e. [5:2] == 0xF
@@ -39,7 +39,12 @@ assign addr_top_bit = (addr[5:2] * 32) - 1;
 always_ff @(posedge hclk or negedge hresetn) begin
     if (~hresetn) begin
         // Reset Construction Buffer
-        const_buffer <= {PACKETWIDTH{1'b0}};
+        const_buffer   <= {PACKETWIDTH{1'b0}};
+        // Reset Values
+        data_out_valid <= 1'b0;
+        data_out_last  <= 1'b0;
+        data_out       <= {PACKETWIDTH{1'b0}};
+        last_wr_addr   <= {ADDRWIDTH{1'b0}};
     end else begin
         if (write_en) begin
             // If not (awaiting handshake AND address generates new data payload)

hdl/src/wrapper_ahb_interface.sv

@@ -78,15 +78,18 @@ module wrapper_ahb_interface #(
 
   // ----------------------------------------
   // Internal wires declarations
-   logic                    input_trans_req  = hreadys & hsels & htranss[1] & (~haddrs[ADDRWIDTH-1]);
-   logic                    output_trans_req = hreadys & hsels & htranss[1] & haddrs[ADDRWIDTH-1];
+   logic input_trans_req;
+   logic output_trans_req;
+   
+   assign input_trans_req  = hreadys & hsels & htranss[1] & (~haddrs[ADDRWIDTH-1]);
+   assign output_trans_req = hreadys & hsels & htranss[1] & haddrs[ADDRWIDTH-1];
   // use top bit of address to decifer which channel to communciate with
   // transfer request issued only in SEQ and NONSEQ status and slave is
   // selected and last transfer finish
 
    // Engine Input Signal Generation
-   logic                    input_ahb_read_req  = input_trans_req & (~hwrites);// AHB read request
-   logic                    input_ahb_write_req = input_trans_req &  hwrites;  // AHB write request
+   logic                    input_ahb_read_req;  // AHB read request
+   logic                    input_ahb_write_req; // AHB write request
    logic                    input_update_read_req;    // To update the read enable register
    logic                    input_update_write_req;   // To update the write enable register
 
@@ -96,9 +99,12 @@ module wrapper_ahb_interface #(
 
    logic  [3:0]             input_byte_strobe_reg; // registered output for byte strobe
 
+   assign input_ahb_read_req  = input_trans_req & (~hwrites);// AHB read request
+   assign input_ahb_write_req = input_trans_req &  hwrites;  // AHB write request
+
    // Engine Output Signal Generation
-   logic                    output_ahb_read_req  = output_trans_req & (~hwrites);// AHB read request
-   logic                    output_ahb_write_req = output_trans_req &  hwrites;  // AHB write request
+   logic                    output_ahb_read_req;// AHB read request
+   logic                    output_ahb_write_req;  // AHB write request
    logic                    output_update_read_req;    // To update the read enable register
    logic                    output_update_write_req;   // To update the write enable register
 
@@ -108,6 +114,9 @@ module wrapper_ahb_interface #(
 
    logic  [3:0]             output_byte_strobe_reg; // registered output for byte strobe
 
+   assign                   output_ahb_read_req  = output_trans_req & (~hwrites);// AHB read request
+   assign                   output_ahb_write_req = output_trans_req &  hwrites;  // AHB write request
+
    logic  [3:0]             byte_strobe_nxt; // next state for byte_strobe_reg
 
     // Channel Selection Register
@@ -125,10 +134,10 @@ module wrapper_ahb_interface #(
     end else begin 
         if (input_trans_req) begin
             input_addr_reg  <= haddrs[ADDRWIDTH-2:0]; // register address for data phase
-            channel_sel   <= haddrs[ADDRWIDTH-1];
+            channel_sel     <= haddrs[ADDRWIDTH-1];
         end else if (output_trans_req) begin
             output_addr_reg <= haddrs[ADDRWIDTH-2:0]; // register address for data phase
-            channel_sel   <= haddrs[ADDRWIDTH-1];
+            channel_sel     <= haddrs[ADDRWIDTH-1];
         end
     end
   end
@@ -158,10 +167,10 @@ module wrapper_ahb_interface #(
   end
 
   // register write signal generation
-  assign input_update_write_req = input_ahb_write_req |( input_write_en_reg & hreadys);  // Update write enable control if
+  assign input_update_write_req = input_ahb_write_req | (input_write_en_reg & hreadys);  // Update write enable control if
                                  //  1. When there is a valid write request
                                  //  2. When there is an active write, update it at the end of transfer (HREADY=1)
-  assign output_update_write_req = output_ahb_write_req |( output_write_en_reg & hreadys);  // Update write enable control if
+  assign output_update_write_req = output_ahb_write_req | (output_write_en_reg & hreadys);  // Update write enable control if
                                  //  1. When there is a valid write request
                                  //  2. When there is an active write, update it at the end of transfer (HREADY=1)
 

hdl/src/wrapper_top.sv

@@ -103,44 +103,44 @@ module wrapper_top #(
 
   // Interface block to convert AHB transfers to Register transfers to engine input/output channels
   // engine Input/Output Channels
-  wrapper_ahb_interface
-   #(.ADDRWIDTH (ADDRWIDTH))
-    u_wrapper_ahb_interface (
-  .hclk         (HCLK),
-  .hresetn      (HRESETn),
-
-  // Input slave port: 32 bit data bus interface
-  .hsels        (HSELS),
-  .haddrs       (HADDRS),
-  .htranss      (HTRANSS),
-  .hsizes       (HSIZES),
-  .hwrites      (HWRITES),
-  .hreadys      (HREADYS),
-  .hwdatas      (HWDATAS),
-
-  .hreadyouts   (HREADYOUTS),
-  .hresps       (HRESPS),
-  .hrdatas      (HRDATAS),
-
-   // Register interface - Accelerator Engine Input
-  .input_addr        (input_addr),
-  .input_read_en     (input_read_en),
-  .input_write_en    (input_write_en),
-  .input_byte_strobe (input_byte_strobe),
-  .input_wdata       (input_wdata),
-  .input_rdata       (input_rdata),
-  .input_wready      (input_wready),
-  .input_rready      (input_rready),
-
-   // Register interface - Accelerator Engine Output
-  .output_addr        (output_addr),
-  .output_read_en     (output_read_en),
-  .output_write_en    (output_write_en),
-  .output_byte_strobe (output_byte_strobe),
-  .output_wdata       (output_wdata),
-  .output_rdata       (output_rdata),
-  .output_wready      (output_wready),
-  .output_rready      (output_rready)
+  wrapper_ahb_interface #(
+    ADDRWIDTH
+   ) u_wrapper_ahb_interface (
+    .hclk         (HCLK),
+    .hresetn      (HRESETn),
+
+    // Input slave port: 32 bit data bus interface
+    .hsels        (HSELS),
+    .haddrs       (HADDRS),
+    .htranss      (HTRANSS),
+    .hsizes       (HSIZES),
+    .hwrites      (HWRITES),
+    .hreadys      (HREADYS),
+    .hwdatas      (HWDATAS),
+
+    .hreadyouts   (HREADYOUTS),
+    .hresps       (HRESPS),
+    .hrdatas      (HRDATAS),
+
+    // Register interface - Accelerator Engine Input
+    .input_addr        (input_addr),
+    .input_read_en     (input_read_en),
+    .input_write_en    (input_write_en),
+    .input_byte_strobe (input_byte_strobe),
+    .input_wdata       (input_wdata),
+    .input_rdata       (input_rdata),
+    .input_wready      (input_wready),
+    .input_rready      (input_rready),
+
+    // Register interface - Accelerator Engine Output
+    .output_addr        (output_addr),
+    .output_read_en     (output_read_en),
+    .output_write_en    (output_write_en),
+    .output_byte_strobe (output_byte_strobe),
+    .output_wdata       (output_wdata),
+    .output_rdata       (output_rdata),
+    .output_wready      (output_wready),
+    .output_rready      (output_rready)
   );
 
   wrapper_ahb_deconstruct
@@ -166,10 +166,16 @@ module wrapper_top #(
   .data_out_ready (data_out_ready)
   );
 
-    // Input Word Combiner
   //-----------------------------------------------------------
   //Module logic end
   //----------------------------------------------------------
+
+  //---------------------
+  //Test Logic
+  //---------------------
+  assign data_out_ready = 1'b1;
+  assign output_wready = 1'b1;
+  assign output_rready = 1'b1;
 `ifdef ARM_AHB_ASSERT_ON
 
  `include "std_ovl_defines.h"

hdl/verif/tb_wrapper_top.sv

@@ -120,7 +120,7 @@ always
 // 0x11000000 - 0x11000FFF : HSEL #1 - SRAM
 // Other addresses         : HSEL #2 - Default slave
 
-  assign hsel0 = (haddr[31:12] == 20'h10000)? 1'b1:1'b0;
+  assign hsel0 = (haddr[31:20] == 20'h600)? 1'b1:1'b0;
   assign hsel1 = (haddr[31:12] == 20'h11000)? 1'b1:1'b0;
   assign hsel2 = (hsel0|hsel1)? 1'b0:1'b1;