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  • a0d02b4f5cf1f667bbefb8eb2403dc36e6f98f6c
  • main default protected
  • QSPI-map
  • feat_dmax4
  • nanosoc_accel-2023
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Created with Raphaël 2.2.04Dec23Nov21625Oct131243230Sep2928272129Aug24211419Jul12111065432130Jun2928232226May221716151094329Apr282726121165328Mar24222120161528Feb2722211716133131Jan271716111096548Dec715Febupdated nanosoc testbench ready for test mode supportRestructured flists to remove DMA from QSupdate QS testbench to fix binary code uploadsfix an off-by-one error in ADP file preloadadd code preload to ADP stream palyback ready for netlistinvert GWEN and WEN signalling for Arm RegFilesRestructure and update ASIC flowsAdd DS6 support still needs workAdd copy of nanosoc DMA350 address mappingRemove secworks from repositoryAdd Precompiled testcodesDM230 default to allow AES128 project to workUpdate synopsys synthesis flowimproved (PL230) DMA testupdated html_gen filelist_compile to strip out .sv files with --html command line optionVCS simulation support updateadd asic_lib_techfix $ to $env for tcl flistsadd -v argument support for verilog .vc file listsUpdate nanosocUpdate simulate_hello to use test_nanosoc over test_aes128add dma 350 config to set_envupdate nanosocUpdate to include DMA350update to latest nanosoc_tech(Quickstart) chip level CLK and TEST pins (replace XTAL1, XTAL2)chip level CLK and TEST pins (replace XTAL1, XTAL2)Update READMEclean up DM230 ahb_ctrl changesenable the PL230_PLUS_PTR_CACHE mode enhancementadd new KRIA VR260 and KV260 Xilinx FPGA make targetsEnhanced soclabs DMA230 software compatible DMA engineUpdated ASIC flowupdate asic flowUpdate ASIC flowfix html generation (as no accelerator RTL), and add README usage instructionsADD ASIC flow for flistsMerge branch 'main' into 'main'Update nanosoc and soctoolsupdate stdin to use USRT RX stream channel to run diagnostic ADP C-tests