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Created with Raphaël 2.2.04Apr7Mar4Feb28Jan2116Dec157Nov29Oct8743212Sep17Jul315Jun22May2116Jan1511108712Dec65423Nov21625Oct131243230Sep2928272129Aug24211419Jul12111065432130Jun2928232226May221716151094329Apr282726121165328Mar24222120161528Feb2722211716133131Jan271716111096548Dec715FebAdd TSMC 16nm initial flowmainmainIntegrate AHB XiP QSPI into nanosoc branchQSPI-mapQSPI-mapupdate to latest nanosoc extio interfaceupdate project with nanosoc extio synthesis fixupgrade to use nanosoc with extio8x4 with enhanced arbitrationupdated nanosoc QuickStart testbench to address QS regression failureupdate to latest nanosoc tests to fix interrupt_demo test failureupgrade project to new nanosoc dataio channel extensionUpdate docs for EXP sram preloadAdd memory preload for EXP srams in simulationsubrepo updateupdate vivado pinmap pullups across zynq platformsnanosoc_accel-2…nanosoc_accel-2023update vivado nanosoc_design scripts for 2024_1 (and 2021_1) versionsSeperate FPGA and behavioural flistsupport FPGA targets other than zynqplusupdate FPGA targets for extio commsupdate and simplify zcu104 extio validation to 40MHzupdate the FPGA top level for extio controllerupdate the FPGA IP components for extio controllerzcu104 target extio testbenchfix up QuickStart testbench for extio validationfix up QuickStart extio flistfix up QuickStart tb fileistexclude uart tests while getting extio validatedexclude uart tests while getting extio validatedmerge extio8x4 interface and testbenchesupdate zcu104 fpga target pre extio integrationUpdate .gitmodulesInitial update for 65nm and 28nm flows and addition of Synopsys SLMUpdate .gitmodulesUpdate projbranchfeat_dmax4feat_dmax4Update .gitmodulesfeat_dmax4 branch support for DMA0 + DMA1/2/3 busmatrixMove nanosoc.config to top level projectUpdate nanosoc configuration methodUpdate regression_nanosoc.shAdd support for ADP program load in simulationAdd Fast loader to nanosoc testbenchUpdate README.mdremove ASIC_TEST_PORTS dependence at chip level