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  • 18c9446a365f9e5dc097d46a9f43bfaad6ac652f
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  • QSPI-map
  • feat_dmax4
  • nanosoc_accel-2023
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Created with Raphaël 2.2.07Oct22Sep161512111014Jul26Jun31May1412Apr11847Mar4Feb28Jan2116Dec157Nov29Oct8743212Sep17Jul315Jun22May2116Jan1511108712Dec65423Nov21625Oct131243230Sep2928272129Aug24211419Jul12111065432130Jun2928232226May221716151094329Apr282726121165328Mar24222120161528Feb2722211716133131Jan271716111096548Dec715FebFix Bootrom .v to .svmainmainMerge branch 'dm-global_source-set_env' into 'main'Allowing the sourcing of the set_env to occur from any directory by saving the...Update cadence backend flowRemove GCC target from CI/CDADD CI/CD targets for DS6, GCC and ASIC synthesis + FIX: DS6 compilation errorComment out regressionAdd results artifact regression for CICDRun regression with makeAttempt to fix simulate_regression by adding command after regressionFix setenv so it overwrites autoconfig on source set_env.shAdd environment checker to set_env.sh and fix GCC bootrom compileFix icarus verilog simulationsAdd gate sims support and begin migration of ASIC flow to ASIC flow subrepositoryUpdate TSMC 28nm backend change libraries, timing now working wellUpdate TSMC backend flows, still work in progressupdate nanosoc bootloader dateupgrade to nanosoc_system with extdataio with DMA(230)update nanosoc for FT1248 progrmmable prescalerrepair nanosoc pin_mux functionalityAdd TSMC 16nm initial flowIntegrate AHB XiP QSPI into nanosoc branchQSPI-mapQSPI-mapupdate to latest nanosoc extio interfaceupdate project with nanosoc extio synthesis fixupgrade to use nanosoc with extio8x4 with enhanced arbitrationupdated nanosoc QuickStart testbench to address QS regression failureupdate to latest nanosoc tests to fix interrupt_demo test failureupgrade project to new nanosoc dataio channel extensionUpdate docs for EXP sram preloadAdd memory preload for EXP srams in simulationsubrepo updateupdate vivado pinmap pullups across zynq platformsnanosoc_accel-2…nanosoc_accel-2023update vivado nanosoc_design scripts for 2024_1 (and 2021_1) versionsSeperate FPGA and behavioural flistsupport FPGA targets other than zynqplusupdate FPGA targets for extio commsupdate and simplify zcu104 extio validation to 40MHzupdate the FPGA top level for extio controllerupdate the FPGA IP components for extio controllerzcu104 target extio testbench