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Commit e9d459e1 authored by dam1n19's avatar dam1n19
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ATO2-24: Created Config Synchroniser to sync config data with an ID stream

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hdl/src/sha256_config_sync.sv 0 → 100644
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View file @ e9d459e1
//-----------------------------------------------------------------------------
// SoC Labs Basic SHA-256 Configuration Synchroniser
// A joint work commissioned on behalf of SoC Labs, under Arm Academic Access license.
//
// Contributors
//
// David Mapstone (d.a.mapstone@soton.ac.uk)
//
// Copyright 2023, SoC Labs (www.soclabs.org)
//-----------------------------------------------------------------------------
module sha256_config_sync (
input logic clk,
input logic nrst,
input logic en,
// Synchronous, localised reset
input logic sync_rst,
// ID In and Handshaking
input logic [5:0] id_in,
input logic id_in_last,
input logic id_in_valid,
output logic id_in_ready,
// Config data and Handshaking
input logic [63:0] cfg_in_size,
input logic [1:0] cfg_in_scheme,
input logic cfg_in_last,
input logic cfg_in_valid,
output logic cfg_in_ready,
// Data Out data and Handshaking
output logic [63:0] cfg_out_size,
output logic [1:0] cfg_out_scheme,
output logic [5:0] cfg_out_id,
output logic cfg_out_last,
output logic cfg_out_valid,
input logic cfg_out_ready
);
logic [1:0] state, next_state;
logic next_cfg_in_ready;
logic next_id_in_ready;
logic [63:0] next_cfg_out_size;
logic [1:0] next_cfg_out_scheme;
logic [5:0] next_cfg_out_id;
logic next_cfg_out_last;
logic next_cfg_out_valid;
// State Machine Sequential Logic
always_ff @(posedge clk, negedge nrst) begin
if ((!nrst) | sync_rst) begin
state <= 2'd0;
cfg_out_size <= 64'd0;
cfg_out_scheme <= 2'd0;
cfg_out_id <= 6'd0;
cfg_out_last <= 1'b0;
cfg_out_valid <= 1'b0;
cfg_in_ready <= 1'b0;
id_in_ready <= 1'b0;
end else if (en == 1'b1) begin
state <= next_state;
cfg_out_size <= next_cfg_out_size;
cfg_out_scheme <= next_cfg_out_scheme;
cfg_out_id <= next_cfg_out_id;
cfg_out_last <= next_cfg_out_last;
cfg_out_valid <= next_cfg_out_valid;
cfg_in_ready <= next_cfg_in_ready;
id_in_ready <= next_id_in_ready;
end else begin
cfg_out_valid <= 1'b0;
cfg_in_ready <= 1'b0;
id_in_ready <= 1'b0;
end
end
always_comb begin
// Default
next_state = state;
next_cfg_out_size = cfg_out_size;
next_cfg_out_scheme = cfg_out_scheme;
next_cfg_out_id = cfg_out_id;
next_cfg_out_last = cfg_out_last;
next_cfg_out_valid = cfg_out_valid;
next_cfg_in_ready = cfg_in_ready;
next_id_in_ready = id_in_ready;
// Override
case (state)
2'd0: begin
next_cfg_in_ready = 1'b1;
next_id_in_ready = 1'b1;
next_state = 2'd1;
end
2'd1: begin
// Check outputs can be written to
if (cfg_out_valid && !cfg_out_ready) begin
// If data out is valid and ready is low, there is already data waiting to be transferred
next_cfg_in_ready = 1'b0;
next_id_in_ready = 1'b0;
// If there is no Valid data at the output or there is a valid transfer happening on this clock cycle
end else begin
// These can be overloaded later if data is written to the outputs
next_cfg_out_valid = 1'b0;
next_cfg_in_ready = 1'b1;
next_id_in_ready = 1'b1;
next_cfg_out_last = 1'b0;
// Check cfg input
if (cfg_in_ready && cfg_in_valid) begin
next_cfg_out_last = cfg_in_last;
next_cfg_out_scheme = cfg_in_scheme;
next_cfg_out_size = cfg_in_size;
next_cfg_in_ready = 1'b0;
next_state = 2'd2;
end
// Check Id input
if (id_in_ready && id_in_valid) begin
next_cfg_out_id = id_in;
next_id_in_ready = 1'b0;
next_state = 2'd3;
end
// Check if both inputs handshaked
if ((id_in_ready && id_in_valid) && (cfg_in_ready && cfg_in_valid)) begin
next_cfg_out_valid = 1'b1;
if (!cfg_out_valid && cfg_out_ready) begin
// In case where no valid data and ready is waiting for valid data
// - (will be asserted next cc), guaranteed handshake next cycle
next_cfg_in_ready = 1'b1;
next_cfg_in_ready = 1'b1;
end else begin
next_cfg_in_ready = 1'b0;
next_id_in_ready = 1'b0;
end
next_state = 2'd1;
end
end
end
2'd2: begin // Cfg already handshaked - wait for ID handshake
// These can be overloaded later if data is written to the outputs
next_cfg_out_valid = 1'b0;
next_cfg_in_ready = 1'b0;
next_id_in_ready = 1'b1;
// Check Id input
if (id_in_ready && id_in_valid) begin
next_cfg_out_id = id_in;
next_cfg_out_valid = 1'b1;
if (cfg_out_ready) begin // Guaranteeded Handshake next clock cycle
next_cfg_in_ready = 1'b1;
next_id_in_ready = 1'b1;
end else begin
next_cfg_in_ready = 1'b0;
next_id_in_ready = 1'b0;
end
next_state = 2'd1;
end
end
2'd3: begin // ID already handshaked - wait for config handshake
// These can be overloaded later if data is written to the outputs
next_cfg_out_valid = 1'b0;
next_cfg_in_ready = 1'b1;
next_id_in_ready = 1'b0;
// Check config input
if (cfg_in_ready && cfg_in_valid) begin
next_cfg_out_last = cfg_in_last;
next_cfg_out_scheme = cfg_in_scheme;
next_cfg_out_size = cfg_in_size;
next_cfg_out_valid = 1'b1;
if (cfg_out_ready) begin // Guaranteeded Handshake next clock cycle
next_cfg_in_ready = 1'b1;
next_id_in_ready = 1'b1;
end else begin
next_cfg_in_ready = 1'b0;
next_id_in_ready = 1'b0;
end
next_state = 2'd1;
end
end
endcase
end
endmodule
\ No newline at end of file
hdl/src/sha256_id_issue.sv
+ 1
− 1
View file @ e9d459e1
...@@ -68,7 +68,7 @@ module sha256_id_issue ( ...@@ -68,7 +68,7 @@ module sha256_id_issue (
// Override // Override
case (state) case (state)
1'd0: begin // Get Packet ID Seed 1'd0: begin
next_id_out_cfg_valid = 1'b1; next_id_out_cfg_valid = 1'b1;
next_id_out_buf_valid = 1'b1; next_id_out_buf_valid = 1'b1;
next_state = 1'd1; next_state = 1'd1;
......
hdl/verif/tb_sha256_config_sync.sv 0 → 100644
+ 335
− 0
View file @ e9d459e1
//-----------------------------------------------------------------------------
// SoC Labs Basic SHA-2 Config Synchroniser Testbench
// A joint work commissioned on behalf of SoC Labs, under Arm Academic Access license.
//
// Contributors
//
// David Mapstone (d.a.mapstone@soton.ac.uk)
//
// Copyright 2022, SoC Labs (www.soclabs.org)
//-----------------------------------------------------------------------------
`timescale 1ns/1ns
`include "sha256_config_sync.sv"
module tb_sha256_config_sync;
logic clk;
logic nrst;
logic en;
logic sync_rst;
// Data In data and Handshaking
logic [5:0] id_in;
logic id_in_last;
logic id_in_valid;
logic id_in_ready;
// Config data and Handshaking
logic [63:0] cfg_in_size;
logic [1:0] cfg_in_scheme;
logic cfg_in_last;
logic cfg_in_valid;
logic cfg_in_ready;
// Data Out data and Handshaking
logic [63:0] cfg_out_size;
logic [1:0] cfg_out_scheme;
logic [5:0] cfg_out_id;
logic cfg_out_last;
logic cfg_out_valid;
logic cfg_out_ready;
sha256_config_sync uut (
.clk (clk),
.nrst (nrst),
.en (en),
.sync_rst (sync_rst),
.id_in (id_in),
.id_in_last (id_in_last),
.id_in_valid (id_in_valid),
.id_in_ready (id_in_ready),
.cfg_in_size (cfg_in_size),
.cfg_in_scheme (cfg_in_scheme),
.cfg_in_last (cfg_in_last),
.cfg_in_valid (cfg_in_valid),
.cfg_in_ready (cfg_in_ready),
.cfg_out_size (cfg_out_size),
.cfg_out_scheme (cfg_out_scheme),
.cfg_out_id (cfg_out_id),
.cfg_out_last (cfg_out_last),
.cfg_out_valid (cfg_out_valid),
.cfg_out_ready (cfg_out_ready));
logic id_in_drive_en;
logic cfg_in_drive_en;
logic cfg_out_drive_ready;
logic [5:0] id_in_queue [$];
logic id_in_last_queue [$];
int id_in_gap_queue [$];
logic id_in_wait_queue;
logic [63:0] cfg_in_size_queue [$];
logic [1:0] cfg_in_scheme_queue [$];
logic cfg_in_last_queue [$];
int cfg_in_gap_queue [$];
logic cfg_in_wait_queue;
logic [63:0] cfg_out_size_queue [$];
logic [1:0] cfg_out_scheme_queue [$];
logic [5:0] cfg_out_id_queue [$];
logic cfg_out_last_queue [$];
int cfg_out_stall_queue [$];
logic cfg_out_wait_queue;
// Handle Valid and Data for id_in
always_ff @(posedge clk, negedge nrst) begin: id_in_valid_drive
if (!nrst) begin
id_in <= 512'd0;
id_in_valid <= 1'b0;
id_in_last <= 1'b0;
id_in_gap <= 0;
id_in_wait_queue <= 1'b1;
end else if (id_in_drive_en) begin
if (id_in_gap > 1) begin
id_in_gap <= id_in_gap -1;
id_in_valid <= 1'b0;
end else begin
id_in_valid <= 1'b1;
end
if (((id_in_valid == 1'b1) && (id_in_ready == 1'b1)) ||
(id_in_wait_queue == 1'b1)) begin
// Data transfer just completed or transfers already up to date
if ((id_in_queue.size() > 0) && (id_in_last_queue.size() > 0) && (id_in_gap_queue.size() > 0)) begin
id_in <= id_in_queue.pop_front();
id_in_last <= id_in_last_queue.pop_front();
if (id_in_gap_queue[0] == 0) begin
id_in_valid <= 1'b1;
end else begin
id_in_valid <= 1'b0;
end
id_in_gap <= id_in_gap_queue.pop_front();
id_in_wait_queue <= 1'b0;
end else begin
// No data currently avaiable in queue to write but transfers up to date
id_in_wait_queue <= 1'b1;
id_in_valid <= 1'b0;
end
end
end
end
// Handle Valid and Data for cfg_in
always_ff @(posedge clk, negedge nrst) begin: cfg_in_valid_drive
if (!nrst) begin
cfg_in_size <= 64'd0;
cfg_in_scheme <= 2'd0;
cfg_in_valid <= 1'b0;
cfg_in_last <= 1'b0;
cfg_in_gap <= 0;
cfg_in_wait_queue <= 1'b1;
end else if (cfg_in_drive_en) begin
if (cfg_in_gap > 1) begin
cfg_in_gap <= cfg_in_gap -1;
cfg_in_valid <= 1'b0;
end else begin
cfg_in_valid <= 1'b1;
end
if (((cfg_in_valid == 1'b1) && (cfg_in_ready == 1'b1)) ||
(cfg_in_wait_queue == 1'b1)) begin
// cfg_in transfer just completed or transfers already up to date
if ((cfg_in_size_queue.size() > 0) && (cfg_in_scheme_queue.size() > 0 ) && (cfg_in_last_queue.size() > 0) && (cfg_in_gap_queue.size() > 0)) begin
cfg_in_size <= cfg_in_size_queue.pop_front();
cfg_in_scheme <= cfg_in_scheme_queue.pop_front();
cfg_in_last <= cfg_in_last_queue.pop_front();
if (cfg_in_gap_queue[0] == 0) begin
cfg_in_valid <= 1'b1;
end else begin
cfg_in_valid <= 1'b0;
end
cfg_in_gap <= cfg_in_gap_queue.pop_front();
cfg_in_wait_queue <= 1'b0;
end else begin
// No data currently avaiable in queue to write but transfers up to date
cfg_in_wait_queue <= 1'b1;
cfg_in_valid <= 1'b0;
end
end
end
end
logic [63:0] cfg_out_size_check;
logic [1:0] cfg_out_scheme_check;
logic [5:0] cfg_out_id_check;
logic cfg_out_last_check;
int id_in_gap;
int cfg_in_gap;
int cfg_out_stall;
int packet_num;
// Handle Output Ready Signal Verification
always @(posedge clk) begin
// Check Override Control on Ready
if (cfg_out_drive_ready) begin
// Count down to zero before enabling Ready
if (cfg_out_stall > 1) begin
cfg_out_stall <= cfg_out_stall - 1;
cfg_out_ready <= 1'b0;
end else begin
// Wait for handshake before updating stall value
if ((cfg_out_valid == 1'b1) && (cfg_out_ready == 1'b1)) begin
if (cfg_out_stall_queue.size() > 0) begin
if (cfg_out_stall_queue[0] == 0) begin
cfg_out_ready <= 1'b1;
end else begin
cfg_out_ready <= 1'b0;
end
cfg_out_stall <= cfg_out_stall_queue.pop_front();
end
// Keep Ready Asserted until handshake seen
end else begin
cfg_out_ready <= 1'b1;
end
end
end else begin
cfg_out_ready <= 1'b0;
end
end
// Handle Output Data Verification
always @(posedge clk) begin
// Check Data on Handshake
if ((cfg_out_valid == 1'b1) && (cfg_out_ready == 1'b1)) begin
// Check Size
assert (cfg_out_size == cfg_out_size_check) else begin
$error("cfg_out_size missmatch! packet %d | recieve: %x != check: %x", packet_num, cfg_out_size, cfg_out_size_check);
$finish;
end
if ($test$plusargs ("DEBUG")) $display("cfg_out_size match! packet %d | recieve: %x == check: %x", packet_num, cfg_out_size, cfg_out_size_check);
// Check Scheme
assert (cfg_out_scheme == cfg_out_scheme_check) else begin
$error("cfg_out_scheme missmatch! packet %d | recieve: %x != check: %x", packet_num, cfg_out_scheme, cfg_out_scheme_check);
$finish;
end
if ($test$plusargs ("DEBUG")) $display("cfg_out_scheme match! packet %d | recieve: %x == check: %x", packet_num, cfg_out_scheme, cfg_out_scheme_check);
// Check ID
assert (cfg_out_id == cfg_out_id_check) else begin
$error("cfg_out_id missmatch! packet %d | recieve: %x != check: %x", packet_num, cfg_out_id, cfg_out_id_check);
$finish;
end
if ($test$plusargs ("DEBUG")) $display("cfg_out_id match! packet %d | recieve: %x == check: %x", packet_num, cfg_out_id, cfg_out_id_check);
// Check Last Flag
assert (cfg_out_last == cfg_out_last_check) else begin
$error("cfg_out_last missmatch! packet %d | recieve: %x != check: %x", packet_num, cfg_out_last, cfg_out_last_check);
$finish;
end
if ($test$plusargs ("DEBUG")) $display("cfg_out_last match! packet %d | recieve: %x == check: %x", packet_num, cfg_out_last, cfg_out_last_check);
// Pop new values
if ((cfg_out_size_queue.size() > 0) && (cfg_out_scheme_queue.size() > 0) && (cfg_out_id_queue.size() > 0) && (cfg_out_last_queue.size() > 0)) begin
cfg_out_size_check <= cfg_out_size_queue.pop_front();
cfg_out_scheme_check <= cfg_out_scheme_queue.pop_front();
cfg_out_id_check <= cfg_out_id_queue.pop_front();
cfg_out_last_check <= cfg_out_last_queue.pop_front();
if (cfg_out_last_check == 1'b1) begin
packet_num <= packet_num + 1;
end
end else begin
$display("Test Passes");
$finish;
end
end
end
// File Reading Variables
int fd; // File descriptor Handle
logic [5:0] temp_id_in; // Temporary Input Data Storage
logic temp_id_in_last; // Temporary Input Data Last
int temp_id_in_gap; // Temporary Input Gap
logic [63:0] temp_cfg_in_size; // Temporary cfg size
logic [1:0] temp_cfg_in_scheme; // Temporary cfg scheme
logic temp_cfg_in_last; // Temporary cfg last;
int temp_cfg_in_gap; // Temporary cfg gap;
logic [63:0] temp_cfg_out_size; // Temporary cfg size
logic [1:0] temp_cfg_out_scheme; // Temporary cfg scheme
logic [5:0] temp_cfg_out_id; // Temporary cfg id
logic temp_cfg_out_last; // Temporary cfg last;
int temp_cfg_out_stall; // Temporary cfg stall;
initial begin
$dumpfile("sha256_config_sync.vcd");
$dumpvars(0, tb_sha256_config_sync);
id_in_drive_en = 0;
cfg_in_drive_en = 0;
cfg_out_drive_ready = 0;
// Read input data into Queue
fd = $fopen("../stimulus/testbench/input_id_stim.csv", "r");
while ($fscanf (fd, "%d,%b,%d", temp_id_in, temp_id_in_last, temp_id_in_gap) == 3) begin
id_in_queue.push_back(temp_id_in);
id_in_last_queue.push_back(temp_id_in_last);
id_in_gap_queue.push_back(temp_id_in_gap);
end
$fclose(fd);
// Read input cfg into Queue
fd = $fopen("../stimulus/testbench/input_cfg_stim.csv", "r");
while ($fscanf (fd, "%x,%x,%b,%d", temp_cfg_in_size, temp_cfg_in_scheme, temp_cfg_in_last, temp_cfg_in_gap) == 4) begin
cfg_in_size_queue.push_back(temp_cfg_in_size);
cfg_in_scheme_queue.push_back(temp_cfg_in_scheme);
cfg_in_last_queue.push_back(temp_cfg_in_last);
cfg_in_gap_queue.push_back(temp_cfg_in_gap);
end
$fclose(fd);
// Read output data into Queue
fd = $fopen("../stimulus/testbench/output_cfg_sync_ref.csv", "r");
while ($fscanf (fd, "%x,%x,%d,%b,%d", temp_cfg_out_size, temp_cfg_out_scheme, temp_cfg_out_id, temp_cfg_out_last, temp_cfg_out_stall) == 5) begin
cfg_out_size_queue.push_back(temp_cfg_out_size);
cfg_out_scheme_queue.push_back(temp_cfg_out_scheme);
cfg_out_id_queue.push_back(temp_cfg_out_id);
cfg_out_last_queue.push_back(temp_cfg_out_last);
cfg_out_stall_queue.push_back(temp_cfg_out_stall);
end
$fclose(fd);
// Initialise First Checking Values
cfg_out_size_check = cfg_out_size_queue.pop_front();
cfg_out_scheme_check = cfg_out_scheme_queue.pop_front();
cfg_out_id_check = cfg_out_id_queue.pop_front();
cfg_out_last_check = cfg_out_last_queue.pop_front();
cfg_out_stall = cfg_out_stall_queue.pop_front();
// Defaultly enable Message Builder
en = 1;
// Defaultly set Sync Reset Low
sync_rst = 0;
#20 nrst = 1;
#20 nrst = 0;
#20 nrst = 1;
#20 cfg_in_drive_en = 1;
// Write some data into the config register
# 30 id_in_drive_en = 1;
# 30 cfg_out_drive_ready = 1;
end
initial begin
forever begin
#10 clk = 0;
#10 clk = 1;
end
end
endmodule
\ No newline at end of file
model/py/hash_model.py
+ 28
− 18
View file @ e9d459e1
...@@ -32,8 +32,11 @@ def main(): ...@@ -32,8 +32,11 @@ def main():
random.seed(seed) random.seed(seed)
print(f"Generating {packets} packets using seed: {seed}") print(f"Generating {packets} packets using seed: {seed}")
cfg_words_list = [] in_cfg_words_list = []
cfg_words_gap_list = [] in_cfg_words_gap_list = []
sync_cfg_size_list = []
sync_cfg_id_list = []
sync_cfg_stall_list = []
in_data_words_list = [] in_data_words_list = []
in_data_words_last_list = [] in_data_words_last_list = []
in_data_words_gap_list = [] in_data_words_gap_list = []
...@@ -44,9 +47,7 @@ def main(): ...@@ -44,9 +47,7 @@ def main():
hash_list = [] hash_list = []
hash_stall_list = [] hash_stall_list = []
# ID Lists # ID Lists
id_seed_list = [] id_gap_list = []
id_use_seed_list = []
id_seed_gap_list = [] # Doesn't work in this scenario - ID counter increments when id seed is gapping
expected_id_list = [] expected_id_list = []
expected_id_stall_list = [] expected_id_stall_list = []
...@@ -56,14 +57,18 @@ def main(): ...@@ -56,14 +57,18 @@ def main():
# Gapping - Period to wait before taking Input Valid High # Gapping - Period to wait before taking Input Valid High
# Stalling - Period to wait before taking Output Read High # Stalling - Period to wait before taking Output Read High
if gap_limit > 0: if gap_limit > 0:
cfg_words_gap_list.append(random.randrange(0,gap_limit)) id_gap_list.append(random.randrange(0,gap_limit))
in_cfg_words_gap_list.append(random.randrange(0,gap_limit))
else: else:
cfg_words_gap_list.append(0) id_gap_list.append(0)
in_cfg_words_gap_list.append(0)
if stall_limit > 0: if stall_limit > 0:
hash_stall_list.append(random.randrange(0,stall_limit)) hash_stall_list.append(random.randrange(0,stall_limit))
sync_cfg_stall_list.append(random.randrange(0,stall_limit))
else: else:
hash_stall_list.append(0) hash_stall_list.append(0)
sync_cfg_stall_list.append(0)
# Generate expected output in 512 bit chunks # Generate expected output in 512 bit chunks
cfg_size = math.ceil(random.randint(0,pow(2,14))/8)*8 cfg_size = math.ceil(random.randint(0,pow(2,14))/8)*8
...@@ -80,12 +85,9 @@ def main(): ...@@ -80,12 +85,9 @@ def main():
else: else:
id_stall_value = 0 id_stall_value = 0
if gap_limit > 0:
id_seed_gap_list.append(random.randrange(0,gap_limit))
else:
id_seed_gap_list.append(0)
expected_id_list.append(id_value) expected_id_list.append(id_value)
sync_cfg_id_list.append(id_value)
# Reference Values # Reference Values
id_value += 1 id_value += 1
...@@ -138,7 +140,8 @@ def main(): ...@@ -138,7 +140,8 @@ def main():
message_block_gap.append(0) message_block_gap.append(0)
message_block_last[-1] = "1" message_block_last[-1] = "1"
cfg_words_list.append(cfg_size_str) in_cfg_words_list.append(cfg_size_str)
sync_cfg_size_list.append(cfg_size_str)
in_data_words_list += in_data_words in_data_words_list += in_data_words
in_data_words_last_list += in_data_words_last in_data_words_last_list += in_data_words_last
in_data_words_gap_list += in_data_words_gap in_data_words_gap_list += in_data_words_gap
...@@ -154,10 +157,10 @@ def main(): ...@@ -154,10 +157,10 @@ def main():
# Write out Input ID Seed to Text File # Write out Input ID Seed to Text File
input_header = ["id_seed", "use_seed", "last"] input_header = ["id_seed", "use_seed", "last"]
with open(os.environ["SHA_2_ACC_DIR"] + "/simulate/stimulus/testbench/" + "input_id_seed_stim.csv", "w", encoding="UTF8", newline='') as f: with open(os.environ["SHA_2_ACC_DIR"] + "/simulate/stimulus/testbench/" + "input_id_stim.csv", "w", encoding="UTF8", newline='') as f:
writer = csv.writer(f) writer = csv.writer(f)
for idx, word in enumerate(id_seed_list): for idx, word in enumerate(expected_id_list):
writer.writerow([word, id_use_seed_list[idx], "1"]) writer.writerow([expected_id_list[idx], "1", id_gap_list[idx]])
# Write out Output ID Values to Text File # Write out Output ID Values to Text File
input_header = ["expected_id_value, id_last, stall_value"] input_header = ["expected_id_value, id_last, stall_value"]
...@@ -177,8 +180,15 @@ def main(): ...@@ -177,8 +180,15 @@ def main():
input_header = ["input_cfg_size", "input_cfg_scheme", "input_cfg_last"] input_header = ["input_cfg_size", "input_cfg_scheme", "input_cfg_last"]
with open(os.environ["SHA_2_ACC_DIR"] + "/simulate/stimulus/testbench/" + "input_cfg_stim.csv", "w", encoding="UTF8", newline='') as f: with open(os.environ["SHA_2_ACC_DIR"] + "/simulate/stimulus/testbench/" + "input_cfg_stim.csv", "w", encoding="UTF8", newline='') as f:
writer = csv.writer(f) writer = csv.writer(f)
for idx, word in enumerate(cfg_words_list): for idx, word in enumerate(in_cfg_words_list):
writer.writerow(["{0:x}".format(int(word, 2)), "0", "1", cfg_words_gap_list[idx]]) writer.writerow(["{0:x}".format(int(word, 2)), "0", "1", in_cfg_words_gap_list[idx]])
# Write out Cfg sync reference to Text File
input_header = ["input_cfg_size", "input_cfg_scheme", "input_cfg_last"]
with open(os.environ["SHA_2_ACC_DIR"] + "/simulate/stimulus/testbench/" + "output_cfg_sync_ref.csv", "w", encoding="UTF8", newline='') as f:
writer = csv.writer(f)
for idx, word in enumerate(sync_cfg_size_list):
writer.writerow(["{0:x}".format(int(word, 2)), "0", sync_cfg_id_list[idx], "1", sync_cfg_stall_list[idx]])
# Write out Expected output to text file # Write out Expected output to text file
output_header = ["output_data", "output_data_last"] output_header = ["output_data", "output_data_last"]
......
simulate/stimulus/testbench/input_cfg_stim.csv
+ 96
− 96
View file @ e9d459e1
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simulate/stimulus/testbench/input_data_stim.csv
+ 1485
− 1580
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simulate/stimulus/testbench/input_id_stim.csv 0 → 100644
+ 100
− 0
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simulate/stimulus/testbench/input_message_block_stim.csv
+ 1503
− 1591
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simulate/stimulus/testbench/output_cfg_sync_ref.csv 0 → 100644
+ 100
− 0
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simulate/stimulus/testbench/output_hash_ref.csv
+ 97
− 97
View file @ e9d459e1
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simulate/stimulus/testbench/output_id_ref.csv
+ 59
− 59
View file @ e9d459e1
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simulate/stimulus/testbench/output_message_block_ref.csv
+ 1506
− 1594
View file @ e9d459e1
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