SOC1-124: Restructured environment setup and environment variable names

CHIPKIT @ 67241692

-Subproject commit 89226d95cde43401ac3773c73049f4e623baeac6
+Subproject commit 672416929813708f48e5376c8de00a4f7a69aa9a

accelerator-wrapper @ 7a5fe702

-Subproject commit 8cdaed6e4eb5b9a56d6a44bdec1ef1348138efe8
+Subproject commit 7a5fe7024c3d2be951242c81f15aa743fca5faa8

env/dependency_env.sh

+#-----------------------------------------------------------------------------
+# SoC Labs Dependency Repository Environment Setup Script
+# A joint work commissioned on behalf of SoC Labs, under Arm Academic Access license.
+#
+# Contributors
+#
+# David Mapstone (d.a.mapstone@soton.ac.uk)
+#
+# Copyright  2023, SoC Labs (www.soclabs.org)
+#-----------------------------------------------------------------------------
+#!/bin/bash
+
+#-----------------------------------------------------------------------------
+# Technologies
+#-----------------------------------------------------------------------------
+
+# Accelerator Engine
+export SECWORKS_SHA2_TECH_DIR="$PROJECT_DIR/secworks-sha256"
+
+# Accelerator Wrapper
+export WRAPPER_TECH_DIR="$PROJECT_DIR/accelerator-wrapper"
+
+# NanoSoC
+export NANOSOC_TECH_DIR="$PROJECT_DIR/nanosoc"
+
+#-----------------------------------------------------------------------------
+# Flows
+#-----------------------------------------------------------------------------
+
+# CHIPKIT - Register Generation
+export CHIPKIT_FLOW_DIR="$PROJECT_DIR/CHIPKIT"
+
+# SoCSim - Basic Simulation Flow Wrapper
+export SOCSIM_FLOW_DIR="$PROJECT_DIR/socsim"
\ No newline at end of file

flist/ahb_ip.flist

@@ -16,9 +16,9 @@
 +libext+.v+.vlib
 
 // =============    Accelerator Module search path    =============
--y $(SOC_TOP_DIR)/cmsdk/ip/
-+incdir+$(SOC_TOP_DIR)/hdl/ip/
+-y $(PROJECT_DIR)/cmsdk/ip/
++incdir+$(PROJECT_DIR)/hdl/ip/
 
-$(SOC_TOP_DIR)/cmsdk/ip/cmsdk_ahb_default_slave.v
-$(SOC_TOP_DIR)/cmsdk/ip/cmsdk_ahb_slave_mux.v
-// $(SOC_TOP_DIR)/cmsdk/ip/cmsdk_ahb_ram_beh.v
\ No newline at end of file
+$(PROJECT_DIR)/cmsdk/ip/cmsdk_ahb_default_slave.v
+$(PROJECT_DIR)/cmsdk/ip/cmsdk_ahb_slave_mux.v
+// $(PROJECT_DIR)/cmsdk/ip/cmsdk_ahb_ram_beh.v
\ No newline at end of file

flist/ahb_vip.flist

@@ -16,9 +16,9 @@
 +libext+.v+.vlib
 
 // =============    Accelerator Module search path    =============
--y $(SOC_TOP_DIR)/cmsdk/vip/
-+incdir+$(SOC_TOP_DIR)/cmsdk/vip/
+-y $(PROJECT_DIR)/cmsdk/vip/
++incdir+$(PROJECT_DIR)/cmsdk/vip/
 
-$(SOC_TOP_DIR)/cmsdk/vip/cmsdk_ahb_fileread_master32.v
-$(SOC_TOP_DIR)/cmsdk/vip/cmsdk_ahb_fileread_funnel.v
-$(SOC_TOP_DIR)/cmsdk/vip/cmsdk_ahb_filereadcore.v
\ No newline at end of file
+$(PROJECT_DIR)/cmsdk/vip/cmsdk_ahb_fileread_master32.v
+$(PROJECT_DIR)/cmsdk/vip/cmsdk_ahb_fileread_funnel.v
+$(PROJECT_DIR)/cmsdk/vip/cmsdk_ahb_filereadcore.v
\ No newline at end of file

flist/primatives.flist

@@ -16,7 +16,7 @@
 +libext+.v+.vlib
 
 // =============    Accelerator Module search path    =============
--y $(SOC_TOP_DIR)/primatives/src/
-+incdir+$(SOC_TOP_DIR)/primatives/src/
+-y $(PROJECT_DIR)/primatives/src/
++incdir+$(PROJECT_DIR)/primatives/src/
 
-$(SOC_TOP_DIR)/primatives/src/fifo_vr.sv
+$(PROJECT_DIR)/primatives/src/fifo_vr.sv

flist/secwork_sha25_stream.flist

+//-----------------------------------------------------------------------------
+// Secworks SHA2 Accelerator AXI-Stream Filelist
+// A joint work commissioned on behalf of SoC Labs, under Arm Academic Access license.
+//
+// Contributors
+//
+// David Mapstone (d.a.mapstone@soton.ac.uk)
+//
+// Copyright � 2021-3, SoC Labs (www.soclabs.org)
+//-----------------------------------------------------------------------------
+//-----------------------------------------------------------------------------
+// Abstract : Verilog Command File for Accelerator AXI Stream IP
+//-----------------------------------------------------------------------------
+
+// ============= Verilog library extensions ===========
++libext+.v+.vlib
+
+// =============    Accelerator Module search path    =============
+-y $(SECWORKS_SHA2_TECH_DIR)/src/rtl/
++incdir+$(SECWORKS_SHA2_TECH_DIR)/src/rtl/
+ 
+$(SECWORKS_SHA2_TECH_DIR)/src/interfaces/stream/rtl/sha256_stream.v
+
+$(SECWORKS_SHA2_TECH_DIR)/src/rtl/sha256_core.v
+$(SECWORKS_SHA2_TECH_DIR)/src/rtl/sha256_k_constants.v
+$(SECWORKS_SHA2_TECH_DIR)/src/rtl/sha256_w_mem.v

flist/system.flist

@@ -16,7 +16,7 @@
 +libext+.v+.vlib
 
 // =============    Accelerator Module search path    =============
--y $(SOC_TOP_DIR)/system/src/
-+incdir+$(SOC_TOP_DIR)/system/src/
+-y $(PROJECT_DIR)/system/src/
++incdir+$(PROJECT_DIR)/system/src/
 
-$(SOC_TOP_DIR)/system/src/nanosoc_exp.v
\ No newline at end of file
+$(PROJECT_DIR)/system/src/nanosoc_exp.v
\ No newline at end of file

flist/wrapper.flist

@@ -16,8 +16,8 @@
 +libext+.v+.vlib
 
 // =============    Accelerator Module search path    =============
--y $(SOC_TOP_DIR)/wrapper/src/
-+incdir+$(SOC_TOP_DIR)/wrapper/src/
+-y $(PROJECT_DIR)/wrapper/src/
++incdir+$(PROJECT_DIR)/wrapper/src/
 
-$(SOC_TOP_DIR)/wrapper/src/wrapper_secworks_sha256.sv
-$(SOC_TOP_DIR)/wrapper/src/wrapper_digest_filter.sv
+$(PROJECT_DIR)/wrapper/src/wrapper_secworks_sha256.sv
+$(PROJECT_DIR)/wrapper/src/wrapper_digest_filter.sv

flist/wrapper_ip.flist

+//-----------------------------------------------------------------------------
+// Accelerator Wrapper Filelist
+// A joint work commissioned on behalf of SoC Labs, under Arm Academic Access license.
+//
+// Contributors
+//
+// David Mapstone (d.a.mapstone@soton.ac.uk)
+//
+// Copyright � 2021-3, SoC Labs (www.soclabs.org)
+//-----------------------------------------------------------------------------
+//-----------------------------------------------------------------------------
+// Abstract : Verilog Command File for Accelerator Wrapper IP
+//-----------------------------------------------------------------------------
+
+// ============= Verilog library extensions ===========
++libext+.v+.vlib
+
+// =============    Accelerator Module search path    =============
+-y $(WRAPPER_TECH_DIR)/hdl/src/
++incdir+$(WRAPPER_TECH_DIR)/hdl/src/
+
+$(WRAPPER_TECH_DIR)/hdl/src/wrapper_ahb_packet_constructor.sv
+$(WRAPPER_TECH_DIR)/hdl/src/wrapper_ahb_packet_deconstructor.sv
+
+$(WRAPPER_TECH_DIR)/hdl/src/wrapper_addr_calc.sv
+$(WRAPPER_TECH_DIR)/hdl/src/wrapper_data_req.sv
+$(WRAPPER_TECH_DIR)/hdl/src/wrapper_ahb_reg_interface.sv
+// $(WRAPPER_TECH_DIR)/hdl/src/wrapper_ahb_vr_interface.sv
+$(WRAPPER_TECH_DIR)/hdl/src/wrapper_packet_construct.sv
+$(WRAPPER_TECH_DIR)/hdl/src/wrapper_packet_deconstruct.sv

flow/simulators/ivlog_sim.sh

@@ -11,6 +11,6 @@
 
 #!/usr/bin/env bash
 
-mkdir -p $SOC_TOP_DIR/simulate/sim/ 
-iverilog -g2012 -o $SOC_TOP_DIR/simulate/sim/$1.vvp $ACC_WRAPPER_DIR/hdl/verif/tb_$1.sv
-cd $SOC_TOP_DIR/simulate/sim/ && vvp $1.vvp $2
\ No newline at end of file
+mkdir -p $PROJECT_DIR/simulate/sim/ 
+iverilog -g2012 -o $PROJECT_DIR/simulate/sim/$1.vvp $WRAPPER_TECH_DIR/hdl/verif/tb_$1.sv
+cd $PROJECT_DIR/simulate/sim/ && vvp $1.vvp $2
\ No newline at end of file

flow/soc-init

@@ -14,7 +14,7 @@
 
 # Source environment variables for all submodules
 cd $DESIGN_ROOT
-for d in $SOC_TOP_DIR/* ; do
+for d in $PROJECT_DIR/* ; do
     if [ -e "$d/.git" ]; then
         echo $d
         if [ -f "$d/set_env.sh" ]; then

flow/socsim

@@ -15,9 +15,9 @@ DEFAULT_SIMULATOR="ivlog"
 if [[ -z "${SIMULATOR}" ]]; then 
     SIMULATOR=$DEFAULT_SIMULATOR
 fi
-# $SOC_TOP_DIR"/flow/simulators/"$SIMULATOR"_sim.sh" $@
+# $PROJECT_DIR"/flow/simulators/"$SIMULATOR"_sim.sh" $@
 
-for d in $SOC_TOP_DIR/* ; do
+for d in $PROJECT_DIR/* ; do
     if [ -f "$d/.git" ]; then
         if [ -f "$d/simulate/socsim/$1.sh" ]; then
         # If .git file exists - submodule

nanosoc @ 3b65f6f3

-Subproject commit 65925f9cf28b2e2d328fcff94b3296b89cca3ffd
+Subproject commit 3b65f6f388136905c590e9e067222e5f3679e90e

secworks-sha256 @ 0ca2ab83

-Subproject commit edec92f3167b358d58f65a2fad4b7f929d78aeb0
+Subproject commit 0ca2ab834833789eb49f8f61d929a80734b3f990

set_env.sh

@@ -24,26 +24,34 @@ if [ -z $DESIGN_ROOT ]; then
     source $DESIGN_ROOT/set_env.sh
 else
     # Set Environment Variable for this Repository
-    export SOC_TOP_DIR="$(cd -P "$(dirname "${BASH_SOURCE[0]}")" && pwd)"
+    export PROJECT_DIR="$(cd -P "$(dirname "${BASH_SOURCE[0]}")" && pwd)"
 
     # If this Repo is root of workspace
-    if [ $SOC_TOP_DIR = $DESIGN_ROOT ]; then
+    if [ $PROJECT_DIR = $DESIGN_ROOT ]; then
         echo "Design Workspace: $DESIGN_ROOT" 
         export DESIGN_ROOT
         # Set Default Simulator
         export SIMULATOR="ivlog"
     fi
 
-    # Source environment variables for all submodules
-    for d in $SOC_TOP_DIR/* ; do
-        if [ -e "$d/.git" ]; then
-            if [ -f "$d/set_env.sh" ]; then
-            # If .git file exists - submodule
-                source $d/set_env.sh
-            fi
-        fi
-    done
+    # Source dependency environment variable script
+    source $PROJECT_DIR/env/dependency_env.sh
 
     # Add Scripts to Path
-    export PATH="$PATH:/$SOC_TOP_DIR/flow"
+    # "TECH_DIR"
+    while read line; do 
+        eval PATH="$PATH:\$${line}/flow"
+    done <<< "$(awk 'BEGIN{for(v in ENVIRON) print v}' | grep TECH_DIR)"
+
+    # "FLOW_DIR"
+    while read line; do 
+        eval PATH="$PATH:\$${line}/flow"
+    done <<< "$(awk 'BEGIN{for(v in ENVIRON) print v}' | grep FLOW_DIR)"
+
+    # "PROJECT_DIR"
+    while read line; do 
+        eval PATH="$PATH:\$${line}/flow"
+    done <<< "$(awk 'BEGIN{for(v in ENVIRON) print v}' | grep PROJECT_DIR)"
+
+    export PATH
 fi
\ No newline at end of file

simulate/socsim/nanosoc_sha256_hashing_stream.sh

-#-----------------------------------------------------------------------------
-# SoC Labs Cadence Xcelium simulation script for engine testbench
-# A joint work commissioned on behalf of SoC Labs, under Arm Academic Access license.
-#
-# Contributors
-#
-# David Mapstone (d.a.mapstone@soton.ac.uk)
-#
-# Copyright  2022, SoC Labs (www.soclabs.org)
-#-----------------------------------------------------------------------------
-
-#!/usr/bin/env bash
-
-mkdir -p $SOC_TOP_DIR/simulate/sim/
-make run_xm \
-    TESTNAME=hello \
-    ACCELERATOR_VC="-sv -f $ACC_ENGINE_DIR/flist/sha-2-accelerator_src.flist -f $ACC_WRAPPER_DIR/flist/wrapper_ip.flist" \
-    ADP_FILE="$SOC_TOP_DIR/system/stimulus/adp_hash_stim.cmd" \
-    -C $NANOSOC_DIR/Cortex-M0/nanosoc/systems/mcu/rtl_sim
\ No newline at end of file

simulate/socsim/wrapper_secworks_sha256.sh

@@ -12,28 +12,25 @@
 #!/usr/bin/env bash
 
 # Generate Stimulus from stimulus generation Script
-# python3 $ACC_SEC_SHA2_DIR/flow/stimgen.py
+# python3 $SECWORKS_SHA2_TECH_DIR/flow/stimgen.py
 # Create Simulatiom Directory to Run in
-mkdir -p $SOC_TOP_DIR/simulate/sim/ 
-mkdir -p $SOC_TOP_DIR/simulate/sim/wrapper_secworks_sha256
+mkdir -p $PROJECT_DIR/simulate/sim/ 
+mkdir -p $PROJECT_DIR/simulate/sim/wrapper_secworks_sha256
 
-cd $SOC_TOP_DIR/simulate/sim/wrapper_secworks_sha256
+cd $PROJECT_DIR/simulate/sim/wrapper_secworks_sha256
 # Compile Simulation
 xrun \
     -64bit \
     -sv \
     -timescale 1ps/1ps \
     +access+r \
-    -f $SOC_TOP_DIR/flist/wrapper.flist \
-    -f $SOC_TOP_DIR/flist/primatives.flist \
-    -f $SOC_TOP_DIR/flist/ahb_ip.flist \
-    -f $SOC_TOP_DIR/flist/ahb_vip.flist \
-    -f $ACC_SEC_SHA2_DIR/flist/*.flist \
-    -f $ACC_WRAPPER_DIR/flist/wrapper_ip.flist \
-    -xmlibdirname $SOC_TOP_DIR/simulate/sim/wrapper_secworks_sha256 \
-    $SOC_TOP_DIR/wrapper/verif/tb_wrapper_secworks_sha256.sv \
+    -f $PROJECT_DIR/flist/primatives.flist \
+    -f $PROJECT_DIR/flist/wrapper_ip.flist \
+    -f $PROJECT_DIR/flist/ahb_ip.flist \
+    -f $PROJECT_DIR/flist/wrapper.flist \
+    -f $PROJECT_DIR/flist/ahb_vip.flist \
+    -f $PROJECT_DIR/flist/secworks_sha25_stream.flist \
+    -xmlibdirname $PROJECT_DIR/simulate/sim/wrapper_secworks_sha256 \
+    $PROJECT_DIR/wrapper/verif/tb_wrapper_secworks_sha256.sv \
     -gui \
-    -top tb_wrapper_secworks_sha256
-
-# Run Simulation
-# cd $SOC_TOP_DIR/simulate/sim/ && vvp wrapper_sha256_hashing_stream.vvp
\ No newline at end of file
+    -top tb_wrapper_secworks_sha256
\ No newline at end of file

simulate/socsim/wrapper_sha256_hashing_stream.sh

-#-----------------------------------------------------------------------------
-# SoC Labs icarus verilog simulation script for engine testbench
-# A joint work commissioned on behalf of SoC Labs, under Arm Academic Access license.
-#
-# Contributors
-#
-# David Mapstone (d.a.mapstone@soton.ac.uk)
-#
-# Copyright  2022, SoC Labs (www.soclabs.org)
-#-----------------------------------------------------------------------------
-
-#!/usr/bin/env bash
-
-# Generate Stimulus from stimulus generation Script
-python3 $ACC_WRAPPER_DIR/flow/stimgen.py
-# Create Simulatiom Directory to Run in
-mkdir -p $SOC_TOP_DIR/simulate/sim/ 
-# Compile Simulation
-iverilog \
-    -c $SOC_TOP_DIR/flist/wrapper.flist \
-    -c $SOC_TOP_DIR/flist/ahb_ip.flist \
-    -c $SOC_TOP_DIR/flist/ahb_vip.flist \
-    -c $ACC_WRAPPER_DIR/flist/wrapper_ip.flist \
-    -c $ACC_ENGINE_DIR/flist/*.flist \
-    -g2012 \
-    -o $SOC_TOP_DIR/simulate/sim/wrapper_sha256_hashing_stream.vvp \
-    $SOC_TOP_DIR/wrapper/verif/tb_wrapper_sha256_hashing_stream.sv
-# Run Simulation
-cd $SOC_TOP_DIR/simulate/sim/ && vvp wrapper_sha256_hashing_stream.vvp
\ No newline at end of file

simulate/socsim/wrapper_vr_loopback.sh

-#-----------------------------------------------------------------------------
-# SoC Labs icarus verilog simulation script for engine testbench
-# A joint work commissioned on behalf of SoC Labs, under Arm Academic Access license.
-#
-# Contributors
-#
-# David Mapstone (d.a.mapstone@soton.ac.uk)
-#
-# Copyright  2022, SoC Labs (www.soclabs.org)
-#-----------------------------------------------------------------------------
-
-#!/usr/bin/env bash
-
-mkdir -p $SOC_TOP_DIR/simulate/sim/ 
-iverilog -c $ACC_WRAPPER_DIR/flist/accelerator_wrapper.flist -c $ACC_WRAPPER_DIR/flist/ahb_ip.flist -c  -I $ACC_WRAPPER_DIR/hdl/verif/ -I $ACC_WRAPPER_DIR/hdl/verif/submodules -I $ACC_WRAPPER_DIR/hdl/src/ -g2012 -o $SOC_TOP_DIR/simulate/sim/wrapper_vr_loopback.vvp $ACC_WRAPPER_DIR/hdl/verif/tb_wrapper_vr_loopback.sv
-cd $SOC_TOP_DIR/simulate/sim/ && vvp wrapper_vr_loopback.vvp +STIMFILE=$ACC_WRAPPER_DIR/simulate/stimulus/ahb_input_hash_stim.m2d
\ No newline at end of file