Updated Accelerator Subsystem and Filelists

flist/nanosoc/nanosoc_tb.flist

@@ -19,16 +19,17 @@
 +incdir+$(SOCLABS_NANOSOC_TECH_DIR)/verif/verilog/
 
 // - Top-level testbench
-$(SOCLABS_NANOSOC_TECH_DIR)/verif/verilog/nanosoc_tb.v
+$(SOCLABS_NANOSOC_TECH_DIR)/verif/tb/verilog/nanosoc_tb.v
 
 // - Testbench components
-$(SOCLABS_NANOSOC_TECH_DIR)/verif/verilog/nanosoc_clkreset.v
-$(SOCLABS_NANOSOC_TECH_DIR)/verif/verilog/nanosoc_uart_capture.v
+$(SOCLABS_NANOSOC_TECH_DIR)/verif/control/verilog/nanosoc_clkreset.v
 
-$(SOCLABS_NANOSOC_TECH_DIR)/verif/verilog/nanosoc_axi_stream_io_8_txd_from_file.v
-$(SOCLABS_NANOSOC_TECH_DIR)/verif/verilog/nanosoc_ft1248x1_to_axi_streamio_v1_0.v
-$(SOCLABS_NANOSOC_TECH_DIR)/verif/verilog/nanosoc_axi_stream_io_8_rxd_to_file.v
-$(SOCLABS_NANOSOC_TECH_DIR)/verif/verilog/nanosoc_track_tb_iostream.v
-$(SOCLABS_NANOSOC_TECH_DIR)/verif/verilog/nanosoc_ft1248x1_track.v
-$(SOCLABS_NANOSOC_TECH_DIR)/verif/verilog/nanosoc_dma_log_to_file.v
-$(SOCLABS_NANOSOC_TECH_DIR)/verif/verilog/nanosoc_acc_log_to_file.v
\ No newline at end of file
+
+$(SOCLABS_NANOSOC_TECH_DIR)/verif/trace/verilog/nanosoc_uart_capture.v
+$(SOCLABS_NANOSOC_TECH_DIR)/verif/trace/verilog/nanosoc_axi_stream_io_8_txd_from_file.v
+$(SOCLABS_NANOSOC_TECH_DIR)/verif/trace/verilog/nanosoc_ft1248x1_to_axi_streamio_v1_0.v
+$(SOCLABS_NANOSOC_TECH_DIR)/verif/trace/verilog/nanosoc_axi_stream_io_8_rxd_to_file.v
+$(SOCLABS_NANOSOC_TECH_DIR)/verif/trace/verilog/nanosoc_track_tb_iostream.v
+$(SOCLABS_NANOSOC_TECH_DIR)/verif/trace/verilog/nanosoc_ft1248x1_track.v
+$(SOCLABS_NANOSOC_TECH_DIR)/verif/trace/verilog/nanosoc_dma_log_to_file.v
+$(SOCLABS_NANOSOC_TECH_DIR)/verif/trace/verilog/nanosoc_accelerator_ss_logger.v
\ No newline at end of file

nanosoc_tech @ 916c2ada

-Subproject commit 95c9e5c1e07a5442371fbf1a3f2b88d76c62da20
+Subproject commit 916c2ada153b3b45abf65b88727e3cb9528322a1

system/src/accelerator_subsystem.v

 //-----------------------------------------------------------------------------
-// SoC Labs Basic Example Accelerator Wrapper
+// SoC Labs Accelerator Subsystem for SecWorks AES-128 Accelerator
 // A joint work commissioned on behalf of SoC Labs; under Arm Academic Access license.
 //
 // Contributors
@@ -11,46 +11,44 @@
 //-----------------------------------------------------------------------------
 
 module accelerator_subsystem #(
-  parameter SYS_ADDR_W=32,
-  parameter SYS_DATA_W=32,
-  parameter AHBADDRWIDTH=16,
-  parameter INPACKETWIDTH=128,
-  parameter CFGSIZEWIDTH=64,
-  parameter CFGSCHEMEWIDTH=2,
-  parameter OUTPACKETWIDTH=128,
-  parameter CFGNUMIRQ=4
-  ) (
-    input  wire                      HCLK,       // Clock
-    input  wire                      HRESETn,    // Reset
+  parameter SYS_ADDR_W = 32,
+  parameter SYS_DATA_W = 32,
+  parameter ACC_ADDR_W = 16,
+  parameter IRQ_NUM    = 4
+) (
+  input  wire                      HCLK,       // Clock
+  input  wire                      HRESETn,    // Reset
 
-    // AHB connection to Initiator
-    input  wire                      HSEL,
-    input  wire   [SYS_ADDR_W-1:0]   HADDR,
-    input  wire   [1:0]              HTRANS,
-    input  wire   [2:0]              HSIZE,
-    input  wire   [3:0]              HPROT,
-    input  wire                      HWRITE,
-    input  wire                      HREADY,
-    input  wire   [SYS_DATA_W-1:0]   HWDATA,
+  // AHB connection to Initiator
+  input  wire                      HSEL,
+  input  wire   [SYS_ADDR_W-1:0]   HADDR,
+  input  wire   [1:0]              HTRANS,
+  input  wire   [2:0]              HSIZE,
+  input  wire   [3:0]              HPROT,
+  input  wire                      HWRITE,
+  input  wire                      HREADY,
+  input  wire   [SYS_DATA_W-1:0]   HWDATA,
 
-    output wire                      HREADYOUT,
-    output wire                      HRESP,
-    output wire   [SYS_DATA_W-1:0]   HRDATA,
+  output wire                      HREADYOUT,
+  output wire                      HRESP,
+  output wire   [SYS_DATA_W-1:0]   HRDATA,
 
-    // Data Request Signal to DMAC
-    output wire   [1:0]              EXP_DRQ,
-    input  wire   [1:0]              EXP_DLAST,
-    
-    // Interrupts
-    output wire   [CFGNUMIRQ-1:0]    EXP_IRQ
-
-  );
+  // Data Request Signal to DMAC
+  output wire   [1:0]              EXP_DRQ,
+  input  wire   [1:0]              EXP_DLAST,
+  
+  // Interrupts
+  output wire   [IRQ_NUM-1:0]      EXP_IRQ
+);
   
+  //--------------------------------------
+  // AES Accelerator Wrapper
+  //--------------------------------------
   soclabs_ahb_aes128_ctrl u_exp_aes128 (
     .ahb_hclk        (HCLK),
     .ahb_hresetn     (HRESETn),
     .ahb_hsel        (HSEL),
-    .ahb_haddr16     (HADDR[AHBADDRWIDTH-1:0]),
+    .ahb_haddr16     (HADDR[ACC_ADDR_W-1:0]),
     .ahb_htrans      (HTRANS),
     .ahb_hwrite      (HWRITE),
     .ahb_hsize       (HSIZE),
@@ -61,9 +59,9 @@ module accelerator_subsystem #(
     .ahb_hreadyout   (HREADYOUT),
     .ahb_hresp       (HRESP),
     .drq_ipdma128    (EXP_DRQ[0]),
-    .dlast_ipdma128  (1'b0),
+    .dlast_ipdma128  (EXP_DLAST[0]),
     .drq_opdma128    (EXP_DRQ[1]),
-    .dlast_opdma128  (1'b0),
+    .dlast_opdma128  (EXP_DLAST[1]),
     .irq_key128      (EXP_IRQ[0]),
     .irq_ip128       (EXP_IRQ[1]),
     .irq_op128       (EXP_IRQ[2]),