ADD ASIC flow for flists

flist/project/top_ASIC.flist

+//-----------------------------------------------------------------------------
+// Project Top-level Filelist System Filelist
+// A joint work commissioned on behalf of SoC Labs, under Arm Academic Access license.
+//
+// Contributors
+//
+// David Mapstone (d.a.mapstone@soton.ac.uk)
+//
+// Copyright � 2021-3, SoC Labs (www.soclabs.org)
+//-----------------------------------------------------------------------------
+//-----------------------------------------------------------------------------
+// Abstract : Verilog Command File for Top-level Accelerator System
+//-----------------------------------------------------------------------------
+
+// DESIGN_TOP nanosoc_chip
+
+// ============= Verilog library extensions ===========
++libext+.v+.vlib
+
+// =============    System Filelist      =========================
+// - Defines RTL
++incdir+$(SOCLABS_PROJECT_DIR)/system/src/defines
+
+-f $(SOCLABS_PROJECT_DIR)/flist/project/system.flist
+
+// =============    Arm-IP Specific Filelists      =========================
+// - NanoSoC Chip IP
+-f $(SOCLABS_NANOSOC_TECH_DIR)/flist/nanosoc.flist
+
+// - CMSDK IP
+-f $(SOCLABS_PROJECT_DIR)/flist/ahb/ahb_ip.flist
+-f $(SOCLABS_PROJECT_DIR)/flist/apb/apb_ip.flist
\ No newline at end of file

nanosoc_tech @ 4dbe52d4

-Subproject commit de2d26f790a0e489cd277a03a66d41ffb009997f
+Subproject commit 4dbe52d4b0b282a788bc79b5b9954db8aae0b184

soctools_flow @ fbbc1c2b

-Subproject commit 039acb1de1eee8477b2da9d1de7229f9205e38da
+Subproject commit fbbc1c2bf2a8fa1ee4731f5368aba37fce20d2f9