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Commit 5f609746 authored by dam1n19's avatar dam1n19
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Further cleaned up project

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1 merge request!1Changed set_env flow to source script in soctools and breadcrumb left in...
//-----------------------------------------------------------------------------
// Generic Library Filelist
// A joint work commissioned on behalf of SoC Labs, under Arm Academic Access license.
//
// Contributors
//
// David Mapstone (d.a.mapstone@soton.ac.uk)
//
// Copyright � 2021-3, SoC Labs (www.soclabs.org)
//-----------------------------------------------------------------------------
//-----------------------------------------------------------------------------
// Abstract : Verilog Command File for Generic Library
//-----------------------------------------------------------------------------
// ============= Verilog library extensions ===========
+libext+.v+.vlib
// ============= Accelerator Module search path =============
$(SOCLABS_GENERIC_LIB_TECH_DIR)/pads/verilog/PAD_INOUT8MA_NOE.v
$(SOCLABS_GENERIC_LIB_TECH_DIR)/pads/verilog/PAD_VDDIO.v
$(SOCLABS_GENERIC_LIB_TECH_DIR)/pads/verilog/PAD_VSSIO.v
$(SOCLABS_GENERIC_LIB_TECH_DIR)/pads/verilog/PAD_VDDSOC.v
$(SOCLABS_GENERIC_LIB_TECH_DIR)/pads/verilog/PAD_VSS.v
$(SOCLABS_GENERIC_LIB_TECH_DIR)/mem/verilog/SROM_Ax32.v
$(SOCLABS_GENERIC_LIB_TECH_DIR)/sync/verilog/SYNCHRONIZER_EDGES.v
\ No newline at end of file
//-----------------------------------------------------------------------------
// FPGA Memory Filelist
// A joint work commissioned on behalf of SoC Labs, under Arm Academic Access license.
//
// Contributors
//
// David Mapstone (d.a.mapstone@soton.ac.uk)
//
// Copyright � 2021-3, SoC Labs (www.soclabs.org)
//-----------------------------------------------------------------------------
//-----------------------------------------------------------------------------
// Abstract : Verilog Command File for NanoSoC Testbench
//-----------------------------------------------------------------------------
// ============= Verilog library extensions ===========
+libext+.v+.vlib
// ============= NanoSoC Testbench search path =============
// +incdir+$(SOCLABS_FPGA_LIB_TECH_DIR)/sram/verilog/
// - Top-level testbench
$(SOCLABS_FPGA_LIB_TECH_DIR)/sram/verilog/sl_ahb_sram.v
$(SOCLABS_FPGA_LIB_TECH_DIR)/rom/verilog/sl_ahb_rom.v
\ No newline at end of file
......@@ -23,10 +23,10 @@
-f $(SOCLABS_PRIMITIVES_TECH_DIR)/flist/rtl_primitives_ip.flist
// - Generic Pad Library
-f $(SOCLABS_PROJECT_DIR)/flist/generic_lib/generic_lib_ip.flist
-f $(SOCLABS_GENERIC_LIB_TECH_DIR)/flist/generic_lib_ip.flist
// - FPGA sram
-f $(SOCLABS_PROJECT_DIR)/flist/mem/fpga_mem.flist
-f $(SOCLABS_FPGA_LIB_TECH_DIR)/flist/fpga_lib_mem_ip.flist
// - Accelerator Wrapper IP
-f $(SOCLABS_WRAPPER_TECH_DIR)/flist/accelerator_wrapper_ip.flist
......
#-----------------------------------------------------------------------------
# ADP Command File Verification Script
# A joint work commissioned on behalf of SoC Labs, under Arm Academic Access license.
#
# Contributors
#
# David Mapstone (d.a.mapstone@soton.ac.uk)
#
# Copyright � 2021-3, SoC Labs (www.soclabs.org)
#-----------------------------------------------------------------------------
class address_region():
def __init__(self, base, size):
self.base = base
self.size = size
self.end = base + size - 4
class read_word():
def __init__(self, index, region, address, read_data = 0,exp_data = 0):
self.index = index
self.region = region
self.address = int(str(address), 16)
self.read_data = int(str(read_data), 16)
self.exp_data = int(str(exp_data), 16)
def validate(self):
if (self.address >= self.region.base and self.address <= self.region.end):
return True
else:
return False
def check_address(self, address):
# print(f"self: {hex(self.address)} test: {address}")
if (self.address == int(str(address), 16)):
return True
else:
return False
def set_read_data(self, read_data):
self.read_data = int(read_data, 16)
def set_exp_data(self, exp_data):
self.exp_data = int(exp_data, 16)
def verify(self):
assert (self.read_data == self.exp_data)
def adp_verify(adp_input, adp_output, out_log):
# Create Input Region for Accelerator
accel_input_port = address_region(base = 0x6001_0000, size = 0x0000_0800)
accel_output_port = address_region(base = 0x6001_0800, size = 0x0000_0800)
word_list = []
temp_address_buf = 0x0
# Read in adp input
adp_input_lines = open(adp_input, "r").readlines()
idx = 0
for line in adp_input_lines:
line_split = str(line).split()
if len(line_split) > 1:
if line_split[0].lower() == "a":
# Capture Address
temp_address_buf = line_split[1]
if line_split[0].lower() == "r":
temp_read_word = read_word(idx, accel_output_port, temp_address_buf, exp_data = line_split[1])
if temp_read_word.validate():
word_list.append(temp_read_word)
idx += 1
# Read in adp output
adp_output_lines = open(adp_output, "r").readlines()
idx = 0
temp_address_buf = 0x0
for line in adp_output_lines:
line_split = str(line).split()
if len(line_split) > 1:
if line_split[0] == "]A":
# Capture Address
temp_address_buf = line_split[1]
if line_split[0] == "]R":
if word_list[idx].check_address(temp_address_buf):
word_list[idx].set_read_data(line_split[1])
idx += 1
# Perform Verification
for word in word_list:
word.verify()
print(f"Tests Passed on {len(word_list)} reads")
if __name__ == "__main__":
adp_input = "ft1248_ip.log"
adp_output = "ft1248_op.log"
output_log = "verify.log"
adp_verify(adp_input,adp_output,output_log)
#!/usr/bin/env python
import csv, os, tabulate
from enum import Enum
soclabs_header = """;#-----------------------------------------------------------------------------
;# SoC Labs Basic Hashing Accelerator Wrapper Input Stimulus File
;# A joint work commissioned on behalf of SoC Labs, under Arm Academic Access license.
;#
;# Contributors
;#
;# David Mapstone (d.a.mapstone@soton.ac.uk)
;#
;# Copyright 2023, SoC Labs (www.soclabs.org)
;#-----------------------------------------------------------------------------"""
class TransactionType(Enum):
""" Enumerated Types for Transaction Types for ASCII Debug """
READ = 1
WRITE = 2
def __str__(self):
if (self == TransactionType.READ):
return "R"
elif (self == TransactionType.WRITE):
return "W"
class TransactionSize(Enum):
""" Enumerated Types for Transaction Types for ASCII Debug """
WORD = 1
HALFWORD = 2
def __str__(self):
if (self == TransactionSize.WORD):
return "word"
elif (self == TransactionSize.HALFWORD):
return "halfword"
class InputBlockStruct:
def __init__(self):
self.word_list = []
def word_append(self, word):
self.word_list.append(word)
class InputPacketStruct:
def __init__(self):
self.block_list = []
def block_append(self, block):
self.block_list.append(block)
class WordStruct:
def __init__(self, data, addr, trans, packet_num = 0, block_num = 0, size = TransactionSize.WORD):
self.data = data
self.addr = addr
self.trans = trans
self.packet_num = packet_num
self.block_num = block_num
self.size = size
def adp_output(out_file, word_list):
"""
This function takes a list of 32 bit words and addresses and formats
the data into .cmd format for the ADP module
testbench
"""
data = []
for word in word_list:
if (word.data > 0):
data.append(["a", "{0:#0{1}x}".format(word.addr,10)])
data.append([str(word.trans).lower(), "{0:#0{1}x}".format(word.data,10)])
table_str = tabulate.tabulate(data, tablefmt="plain")
with open(out_file, "w", encoding="UTF8", newline='') as f:
f.write("A\n")
f.write(table_str)
f.write("\n A")
f.write("\nX")
f.write("\n!")
def fri_output(out_file, word_list):
"""
This function takes a list of 32 bit words and addresses and formats
the data into .fri format to be fed into fml2conv.pl script to stimulate
testbench
"""
# Column Names
col_names = ["Transaction", "Address", "Data", "Size"]
data = []
for word in word_list:
if (word.data > 0):
data.append([str(word.trans), "{0:#0{1}x}".format(word.addr,10), "{0:#0{1}x}".format(word.data,10), str(word.size)])
table_str = tabulate.tabulate(data, headers=col_names, tablefmt="plain")
with open(out_file, "w", encoding="UTF8", newline='') as f:
f.write(soclabs_header + "\n;")
f.write(table_str)
f.write("\nQ") # Add End of Simulation Flag
def stimulus_generation(stim_file, ref_file, input_start_address, input_size, output_start_address, output_size, gen_fri=True):
"""
This function takes 32 bit input stimulus file from accelerator model,
calculates write addresses for each word and generates a .fri file which
can be used to stimulate an AHB testbench
"""
fri_file = os.environ["SOCLABS_PROJECT_DIR"] + "/wrapper/stimulus/" + "ahb_input_hash_stim.fri"
if gen_fri:
# Calculate End Address
input_end_address = input_start_address + input_size - 0x4
# print(f"End Address is {hex(end_address)}")
# Open Files
with open(stim_file, "r") as stim:
csvreader = csv.reader(stim, delimiter=",")
stim_list = list(csvreader)
with open(ref_file, "r") as ref:
csvreader = csv.reader(ref, delimiter=",")
ref_list = list(csvreader)
# Initialise Packet Lists
write_packet_list = []
read_packet_list = []
# Initialise Temporary Structures
temppacketstruct = InputPacketStruct()
tempblockstruct = InputBlockStruct()
# Put Write Data into Structs
for i in stim_list:
tempblockstruct.word_append(int(i[0],16))
# If Last Word in Block, Append to Packet and Reset Temporary block structure
if (int(i[1])):
temppacketstruct.block_append(tempblockstruct)
tempblockstruct = InputBlockStruct()
# If Last Block in Packet , Append Packet to Packet List and Reset Temp Packet
if (int(i[2])):
write_packet_list.append(temppacketstruct)
temppacketstruct = InputPacketStruct()
# Put Read Data into Structs
for i in ref_list:
tempblockstruct.word_append(int(i[0],16))
# If Last Word in Block, Append to Packet and Reset Temporary block structure
if (int(i[1])):
temppacketstruct.block_append(tempblockstruct)
tempblockstruct = InputBlockStruct()
# If Last Block in Packet , Append Packet to Packet List and Reset Temp Packet
if (int(i[2])):
read_packet_list.append(temppacketstruct)
temppacketstruct = InputPacketStruct()
# List of Ouptut Transactions
output_word_list = []
# Generate Address for Packet
for packet_num, write_packet in enumerate(write_packet_list):
# Calculate Number of Blocks in First Packet
num_blocks = len(write_packet.block_list)
# Each Write Block Can Contain 16 32-bit Words (512 bits) (0x4 * 16 = 0x40)
# - Work Out Required Size = (0x40 * NumBlocks)
# - Work Out Beginning Address = (end_address + 0x4) - Size
req_write_size = 0x40 * num_blocks
start_write_addr = input_start_address + input_size - req_write_size
# Each Read Block Contains 8 32-bit Words (256 bits) (0x4 * 8 = 0x20)
req_read_size = 0x20
start_read_addr = output_start_address + output_size - req_read_size
# print(f"Packet: {int(packet_num)} | Start Address: {hex(start_write_addr)}")
write_addr = start_write_addr
read_addr = start_read_addr
# Write out Packet containing multiple 512 bit Blocks to Input Port
for block_num, block in enumerate(write_packet.block_list):
for word in block.word_list:
word_data = WordStruct(word, write_addr, TransactionType.WRITE, packet_num, block_num)
output_word_list.append(word_data)
# Increment Address
write_addr += 0x4
# Set Read Packet
read_packet = read_packet_list[packet_num]
# Read Back 256 Bit Packet from Output Port
for block_num, block in enumerate(read_packet.block_list):
for word in block.word_list:
word_data = WordStruct(word, read_addr, TransactionType.READ, packet_num, 0)
output_word_list.append(word_data)
# Increment Address
read_addr += 0x4
# Generate ADP Command File with Write Transactions
adp_file = os.environ["SOCLABS_PROJECT_DIR"] + "/system/stimulus/" + "adp_hash_stim.cmd"
adp_output(adp_file, output_word_list)
# Generate FRI File with Write Transactions
fri_output(fri_file, output_word_list)
# Call fm2conv.pl script
m2d_file = os.environ["SOCLABS_PROJECT_DIR"] + "/wrapper/stimulus/" + "ahb_input_hash_stim.m2d"
os.system(f"fm2conv.pl -busWidth=32 -infile={fri_file} -outfile={m2d_file}")
if __name__ == "__main__":
accelerator_input_address = 0x6001_0000
accelerator_input_size = 0x0000_0400
accelerator_output_address = 0x6001_0400
accelerator_output_size = 0x0000_0400
stim_file = os.environ["SOCLABS_PROJECT_DIR"] + "/wrapper/stimulus/" + "input_block_32bit_stim.csv"
ref_file = os.environ["SOCLABS_PROJECT_DIR"] + "/wrapper/stimulus/" + "output_hash_32bit_ref.csv"
stimulus_generation(stim_file, ref_file, accelerator_input_address, accelerator_input_size, accelerator_output_address, accelerator_output_size, gen_fri=False)
\ No newline at end of file
Subproject commit 97adc447a536dbbc8ce82f5ff144261a4ce69b0f
Subproject commit ab5ecd8c76ce4ce98954c1549555ca88faad973e
Subproject commit 53dca95d66a93333a7e6e8bbbda0696a348da0b5
Subproject commit 9fe199f7c78d66e5a36b568996901b955717c8ab
Subproject commit e13c438900aad29d692c6b4201fee111326cb3a4
Subproject commit a012b7b8cdd7ff9deb9bb78fcf7738a588ae1ad5
#-----------------------------------------------------------------------------
# SoC Labs Simulation script for system level verification
# A joint work commissioned on behalf of SoC Labs, under Arm Academic Access license.
#
# Contributors
#
# David Mapstone (d.a.mapstone@soton.ac.uk)
#
# Copyright 2023, SoC Labs (www.soclabs.org)
#-----------------------------------------------------------------------------
#!/usr/bin/env bash
# Get simulation name from name of script
SIM_NAME=`basename -s .sh "$0"`
# Directory to put simulation files
SIM_DIR=$SOCLABS_PROJECT_DIR/simulate/sim/$SIM_NAME
# Create Directory to put simulation files
mkdir -p $SIM_DIR
cd $SOCLABS_PROJECT_DIR/simulate/sim/system_secworks_sha256
# Compile Simulation
# Call makefile in NanoSoC Repo with options
echo ${2}
make -C $SOCLABS_NANOSOC_TECH_DIR/system bootrom \
SIM_DIR=$SIM_DIR \
#-----------------------------------------------------------------------------
# SoC Labs Simulation script for system level verification
# A joint work commissioned on behalf of SoC Labs, under Arm Academic Access license.
#
# Contributors
#
# David Mapstone (d.a.mapstone@soton.ac.uk)
#
# Copyright 2023, SoC Labs (www.soclabs.org)
#-----------------------------------------------------------------------------
#!/usr/bin/env bash
# Get simulation name from name of script
SIM_NAME=`basename -s .sh "$0"`
# Directory to put simulation files
SIM_DIR=$SOCLABS_PROJECT_DIR/simulate/sim/$SIM_NAME
# Create Directory to put simulation files
mkdir -p $SIM_DIR
cd $SOCLABS_PROJECT_DIR/simulate/sim/system_secworks_sha256
# Compile Simulation
# Call makefile in NanoSoC Repo with options
echo ${2}
make -C $SOCLABS_NANOSOC_TECH_DIR/system run_xm \
SIM_DIR=$SIM_DIR \
ADP_FILE=$SOCLABS_PROJECT_DIR/system/stimulus/adp_hash_stim.cmd \
${@:2}
#-----------------------------------------------------------------------------
# SoC Labs Simulation script for wrapper level verification testbench
# A joint work commissioned on behalf of SoC Labs, under Arm Academic Access license.
#
# Contributors
#
# David Mapstone (d.a.mapstone@soton.ac.uk)
#
# Copyright 2022, SoC Labs (www.soclabs.org)
#-----------------------------------------------------------------------------
#!/usr/bin/env bash
# Generate Stimulus from stimulus generation Script
# python3 $SECWORKS_SHA2_TECH_DIR/flow/stimgen.py
# Create Simulatiom Directory to Run in
mkdir -p $SOCLABS_PROJECT_DIR/simulate/sim/
mkdir -p $SOCLABS_PROJECT_DIR/simulate/sim/wrapper_secworks_sha256
cd $SOCLABS_PROJECT_DIR/simulate/sim/wrapper_secworks_sha256
# Compile Simulation
xrun \
-64bit \
-sv \
-timescale 1ps/1ps \
+access+r \
-f $SOCLABS_PRIMITIVES_TECH_DIR/flist/primatives.flist \
-f $SOCLABS_PROJECT_DIR/flist/wrapper_ip.flist \
-f $SOCLABS_PROJECT_DIR/flist/ahb_ip.flist \
-f $SOCLABS_PROJECT_DIR/flist/apb_ip.flist \
-f $SOCLABS_PROJECT_DIR/flist/wrapper.flist \
-f $SOCLABS_PROJECT_DIR/flist/ahb_vip.flist \
-f $SOCLABS_PROJECT_DIR/flist/secworks_sha25_stream.flist \
-xmlibdirname $SOCLABS_PROJECT_DIR/simulate/sim/wrapper_secworks_sha256 \
$SOCLABS_PROJECT_DIR/wrapper/verif/tb_wrapper_secworks_sha256.sv \
-gui \
-top tb_wrapper_secworks_sha256
\ No newline at end of file
Subproject commit 74d6c1bb134143547eedccefb6393f3759f13fae
Subproject commit f931478ea42e59f54cbf42b49ee96b25dafd4740
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