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Commit 510d240b authored by dam1n19's avatar dam1n19
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Resolve readme merge changes

parents 781b7016 431df191
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...@@ -10,6 +10,7 @@ This Repository contains multiple sub-repositories. In order to clone them with ...@@ -10,6 +10,7 @@ This Repository contains multiple sub-repositories. In order to clone them with
`git clone --recurse https://git.soton.ac.uk/soclabs/aes-128-project.git` `git clone --recurse https://git.soton.ac.uk/soclabs/aes-128-project.git`
## Setting up the Project Environment ## Setting up the Project Environment
---
In order to checkout all the sub-repositories in your project to their branches and set up your local environment variables, from the top-level of this project run: In order to checkout all the sub-repositories in your project to their branches and set up your local environment variables, from the top-level of this project run:
...@@ -51,6 +52,7 @@ This module is expected to be found in `system/src/accelerator_subsystem.v`. ...@@ -51,6 +52,7 @@ This module is expected to be found in `system/src/accelerator_subsystem.v`.
Accelerator wrappers are located in `wrapper/src`. These should instantiate accelerators and can use wrapper components within the `accelerator_wrapper_tech` repository to allow a conversion of valid//ready interfaces to a memory-mapped AHB interface. Accelerator wrappers are located in `wrapper/src`. These should instantiate accelerators and can use wrapper components within the `accelerator_wrapper_tech` repository to allow a conversion of valid//ready interfaces to a memory-mapped AHB interface.
## Running the simulation ## Running the simulation
---
This design instantiates a custom (AMBA-AHB) wrapper around the AES core to implement a memory-mapped 128-bit AES encrypt/decrypt accelerator that can be used as a software-driven peripheral or a semi-autonomous DMA subystem when 128-bit keys and variable length data payloads can be set up as scatter/gather descriptor chains for background processing. This design instantiates a custom (AMBA-AHB) wrapper around the AES core to implement a memory-mapped 128-bit AES encrypt/decrypt accelerator that can be used as a software-driven peripheral or a semi-autonomous DMA subystem when 128-bit keys and variable length data payloads can be set up as scatter/gather descriptor chains for background processing.
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