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SoCLabs
Accelerator Project
Commits
03ae7df6
Commit
03ae7df6
authored
1 year ago
by
Daniel Newbrook
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Re-add default irq and drq on acc_ss
parent
d60b405f
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Pipeline
#10753
passed
1 year ago
Stage: compile
Stage: simulate
Stage: simulate_qs
Stage: build
Stage: deploy
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nanosoc_tech
+1
-1
1 addition, 1 deletion
nanosoc_tech
system/src/accelerator_subsystem.v
+4
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system/src/accelerator_subsystem.v
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5 additions
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nanosoc_tech
@
4343bd1b
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d9c31606
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4343bd1b
Subproject commit
d9c31606eb81b404185c2ca5963a7d7f6a0d42ac
Subproject commit
4343bd1b3321bd3c5f60f33d072ff0b78008da08
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system/src/accelerator_subsystem.v
+
4
−
0
View file @
03ae7df6
...
...
@@ -91,6 +91,10 @@ module accelerator_subsystem #(
// Instantiate your accelerator/wrapper here
//-------------------------------------------
// Default IRQ and DMA REQ
assign
EXP_IRQ
=
2'b00
;
assign
EXP_DRQ
=
2'b00
;
// Default DMA350 stream loopback
`ifdef
DMAC_DMA350
`ifdef
DMA350_STREAM_2
...
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